Abstract: A direct memory access (DMA) controller for controlling memory access operations in a memory. During a memory access operation, the DMA controller executes a chain of DMA commands stored in a memory and having a respective address. The DMA controller can enter a self-linking mode where additional DMA commands can be appended to the end of the command chain without terminating the memory access operation, regardless of whether the last DMA command of the command chain has been executed by the DMA controller. The self-linking mode is entered when a link-address provided by the last DMA command matches a code. The code to cause the DMA controller to enter the self-linking mode may be a link address which points to the last executed DMA command, or alternatively, a predetermined bit pattern. The DMA controller exits the self-linking command and continues the memory access operation upon detecting a new link address for a new DMA command that is to be appended to the command chain.

Abstract: A method for operating a Reduced Instruction Set Computer (RISC) processor that executes normal RISC instructions and special RISC instructions. The method comprises the step of controlling the RISC processor to perform a single operation, using a single functional unit of the RISC processor, in response to each normal RISC instruction. The method also comprises the step of controlling the RISC processor to perform multiple operations, using multiple functional units of the RISC processor in parallel, in response to each special RISC instruction.

Abstract: A method for operating a Reduced Instruction Set Computer (RISC) processor that executes mormal RISC instructions and special RISC instructions. The method comprises the step of controlling the RISC processor to perform a single operation, using a single functional unit for each RISC processor, in response to each normal RISC instruction. The method also comprises the step of controlling the RISC processor to perform multiple operations, using multiple functional units of the RISC processor in parallel, in response to each special RISC instruction.

Abstract: An apparatus and method for performing byte swapping using a direct memory access (DMA) controller is provided. In a computer system, a DMA controller for a peripheral component is coupled to system memory via a bus. The DMA controller receives a command pointer to initiate a memory access operation. The command pointer specifies the location of the first DMA command in a command list to be executed by the DMA controller. Each DMA command includes an address word giving the starting address and length word indicating the number of data words to be accessed in memory. Because the data stored in memory is double-word aligned, the two least significant bits of the length word are not needed to perform the memory access and are instead used to indicate any byte swapping that is to be performed on the data during the memory access. During a memory access, the DMA controller swaps the bytes in each double-word of data as specified by the two least significant bits of the length word.

Abstract: A method for operating a Reduced Instruction Set Computer (RISC) processor that executes normal RISC instructions and special RISC instructions. The method comprises the step of controlling the RISC processor to perform a single operation, using a single functional unit of the RISC processor, in response to each normal RISC instruction. The method also comprises the step of controlling the RISC processor to perform multiple operations, using multiple functional units of the RISC processor in parallel, in response to each special RISC instruction.

Abstract: An apparatus and method for taking data that is presented on a NUBUS in NUBUS format and writing it into a video memory in chunky planar format, is described. The present invention is also useful for performing RGB reads wherein video data is read from the video memory in chunky planar format and is translated into NUBUS format for transmission across the NUBUS. The apparatus comprises a data format translator which is coupled to the NUBUS for translating the RGB data from NUBUS format to chunky planar format. The translated RGB data in chunky planar format is compressed and rearranged as compared to the NUBUS format--resulting in a more efficient utilization of video memory space. An address generator is also coupled to the video memory for calculating the address location in the video memory where the translated RGB data is to be written. The address location is derived from the NUBUS address according to the formula N.sub.start =(3*NAD/4) where N.sub.