Patents by Inventor Mohan R. Nagar
Mohan R. Nagar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9320183Abstract: An apparatus for grounding a chip may be provided. The apparatus may comprise a ground lid, a ground trace, a first substance, and a second substance. The first substance may be configured adhere the ground lid to the ground trace. The second substance may be configured to provide electrical conduction between the ground lid and the ground trace.Type: GrantFiled: October 12, 2013Date of Patent: April 19, 2016Assignee: Cisco Technology, Inc.Inventor: Mohan R. Nagar
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Publication number: 20160064320Abstract: An integrated circuit chip stack and a method for forming the same in which bond pads of an interposer are directly bonded to bond pads of a package substrate using only pre-solder. The interposer can have a bond pad pitch of less than 150 micrometers. The interposer can be an organic interposer. The pro-solder can be melted to make contact with the bond pads of the package substrate and the interposer. After solidifying, the pre-solder can form an electrical connection between a bond pad of the interposer and a bond pad of the package substrate.Type: ApplicationFiled: August 27, 2014Publication date: March 3, 2016Inventors: Li Li, Mohan R. Nagar, Jovica Savic
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Publication number: 20150173177Abstract: A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.Type: ApplicationFiled: February 23, 2015Publication date: June 18, 2015Inventors: Mohan R. Nagar, Kuo-Chuan Liu, Mudasir Ahmad, Bangalore J. Shanker, Jie Xue
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Patent number: 8962388Abstract: A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.Type: GrantFiled: November 9, 2011Date of Patent: February 24, 2015Assignee: Cisco Technology, Inc.Inventors: Mohan R. Nagar, Kuo-Chuan Liu, Mudasir Ahmad, Bangalore J. Shanker, Jie Xue
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Patent number: 8952523Abstract: An integrated circuit package apparatus includes a packaging substrate, an integrated circuit coupled to an upper side of the packaging substrate, an array of contacts coupled to an underside of the packaging substrate for electrically coupling the integrated circuit to a circuit board, and a lid coupled to the upper side of the packaging substrate. In one form, the lid includes a central portion lying on a first plane, corner areas lying on a second plane, and arcuate wall portions disposed between and interconnecting the corner areas and the central portion. Other forms of the lid are provided.Type: GrantFiled: September 27, 2010Date of Patent: February 10, 2015Assignee: Cisco Technology, Inc.Inventors: Mudasir Ahmad, Mohan R. Nagar, Weidong Xie
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Publication number: 20130284796Abstract: In one implementation, a system in package assembly process includes attaching a cladding to a substrate to keep the substrate flat while components are soldered onto the substrate. The cladding may include a supporting member and a clamping member, and the substrate may be received between the clamping member and the supporting member. The clamping member may have a plurality of openings formed therein, and the components may be positioned on the substrate within at least one of the plurality of openings. A predetermined pressure may be applied to the clamping member and/or supporting to keep the substrate flat.Type: ApplicationFiled: April 25, 2012Publication date: October 31, 2013Applicant: Cisco Technology, Inc.Inventors: Mohan R. Nagar, Mudasir Ahmad
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Publication number: 20120113608Abstract: A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.Type: ApplicationFiled: November 9, 2011Publication date: May 10, 2012Applicant: CISCO TECHNOLOGY, INC.Inventors: Mohan R. Nagar, Kuo-Chuan Liu, Mudasir Ahmad, Bangalore J. Shanker, Jie Xue
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Publication number: 20120074557Abstract: An integrated circuit package apparatus comprises a packaging substrate, an integrated circuit coupled to an upper side of the packaging substrate, an array of contacts coupled to an underside of the packaging substrate for electrically coupling the integrated circuit to a circuit board, and a lid coupled to the upper side of the packaging substrate. In one form, the lid includes a central portion lying on a first plane, corner areas lying on a second plane, and arcuate wall portions disposed between and interconnecting the corner areas and the central portion. Other forms of the lid are provided.Type: ApplicationFiled: September 27, 2010Publication date: March 29, 2012Applicant: CISCO TECHNOLOGY, INC.Inventors: Mudasir Ahmad, Mohan R. Nagar, Weidong Xie
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Patent number: 8081484Abstract: A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.Type: GrantFiled: November 30, 2006Date of Patent: December 20, 2011Assignee: Cisco Technology, Inc.Inventors: Mohan R. Nagar, Kuo-Chuan Liu, Mudasir Ahmad, Bangalore J. Shanker, Jie Xue
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Publication number: 20080130241Abstract: A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.Type: ApplicationFiled: November 30, 2006Publication date: June 5, 2008Applicant: Cisco Technology, Inc.Inventors: Mohan R. Nagar, Kuo-Chuan Liu, Mudasir Ahmad, Bangalore J. Shanker, Jie Xue
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Patent number: 7352062Abstract: A packaged integrated circuit including a package substrate having electrical contacts for receiving an integrated circuit. The integrated circuit is electrically connected to the electrical contacts of the package substrate. A stiffener is mounted to the package substrate, where the stiffener has a non-orthogonal cut out in which the integrated circuit is disposed. The edges of the cut out are disposed at no greater a distance from the corners of the integrated circuit than they are from the sides of the integrated circuit.Type: GrantFiled: November 2, 2004Date of Patent: April 1, 2008Assignee: LSI Logic CorporationInventors: Mukul A. Joshi, Mohan R. Nagar, Sarathy Rajagopalan
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Patent number: 6891392Abstract: A probe structure for testing impedance of a package substrate using time domain reflectometry. A connector electrically connects the probe structure to a time domain reflectometry tester, where the connector has a signal conductor and a ground conductor. An electrically conductive cantilever signal pin is electrically connected to the signal conductor. The electrically conductive cantilever signal pin has a tip for making an electrical connection with an electrically conductive structure to be tested on the package substrate. The electrically conductive cantilever signal pin is electrically isolated by and sheathed within a ground shield that is electrically connected to at least one of the ground conductor and electrically conductive cantilever ground pins. The electrically conductive cantilever ground pins are electrically connected to the ground conductor.Type: GrantFiled: February 21, 2003Date of Patent: May 10, 2005Assignee: LSI Logic CorporationInventors: Mohan R. Nagar, Aritharan Thurairajaratnam
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Publication number: 20040239350Abstract: Probe cards for measuring package interconnect impedance. A first probe card includes a package having solder balls on a first surface, and an electrically conductive material on a second surface. The electrically conductive surface is configured to electrically contact bumps on the substrate. The solder balls are mountable to a test head inter phase board of the tester. The probe card does not have any probe pins, and is configured to make electrical contact with bumps on the substrate without using probe pins. A second probe card includes a substrate with solder balls on one side and solder on pad (SOP) on the other side. Vertical probe pins contact the SOP and act as an interface between a tester and solder bumps on a wafer.Type: ApplicationFiled: October 23, 2003Publication date: December 2, 2004Inventors: Mohan R. Nagar, Kishor Desai, Shirish Shah
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Patent number: 6825556Abstract: A packaged integrated circuit including a package substrate having electrical contacts for receiving an integrated circuit. The integrated circuit is electrically connected to the electrical contacts of the package substrate. A stiffener is mounted to the package substrate, where the stiffener has a non-orthogonal cut out in which the integrated circuit is disposed. The edges of the cut out are disposed at no greater a distance from the corners of the integrated circuit than they are from the sides of the integrated circuit.Type: GrantFiled: October 15, 2002Date of Patent: November 30, 2004Assignee: LSI Logic CorporationInventors: Mukul A. Joshi, Mohan R. Nagar, Sarathy Rajagopalan
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Publication number: 20040164758Abstract: A probe structure for testing impedance of a package substrate using time domain reflectometry. A connector electrically connects the probe structure to a time domain reflectometry tester, where the connector has a signal conductor and a ground conductor. An electrically conductive cantilever signal pin is electrically connected to the signal conductor. The electrically conductive cantilever signal pin has a tip for making an electrical connection with an electrically conductive structure to be tested on the package substrate. The electrically conductive cantilever signal pin is electrically isolated by and sheathed within a ground shield that is electrically connected to at least one of the ground conductor and electrically conductive cantilever ground pins. The electrically conductive cantilever ground pins are electrically connected to the ground conductor.Type: ApplicationFiled: February 21, 2003Publication date: August 26, 2004Inventors: Mohan R. Nagar, Aritharan Thurairajaratnam
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Publication number: 20040070402Abstract: A probe structure with a connector connecting the probe structure to a time domain reflectometry tester, where the connector has a signal conductor and a ground conductor. A back side layer is connected to the connector. A probe side layer with contacts is sandwiched with the back side layer in a layered substrate. The probe side layer has a centrally disposed signal contact and surrounding ground contacts. A conductive layer is disposed between the back side layer and the probe side layer. The conductive layer is connected to the ground conductor of the connector and to the ground contacts of the probe side layer contacts. A via extends from the back side layer to the probe side layer. The via is connected to the signal conductor of the connector, and is also connected to the centrally disposed signal contact of the probe side layer contacts. The via does not make connection with the conductive layer.Type: ApplicationFiled: October 9, 2002Publication date: April 15, 2004Inventors: Aritharan Thurairajaratnam, Mohan R. Nagar
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Publication number: 20040069216Abstract: A pickup head for engaging an integrated circuit from a first side. The pickup head can dip solder bumps disposed on an opposing second side of the integrated circuit into a layer of flux on a flat surface in a uniform manner. An arm attaches the pickup head to a mobility unit, and a retainer selectively retains the first side of the integrated circuit against the pickup head. A pivot is disposed between the arm and the retainer, and enables the retainer to pivot and the integrated circuit to freely align with the flat surface in such a manner that as many of the solder bumps as possible are in contact with the flat surface, regardless of variations in heights of the solder bumps. The solder bumps are thereby more uniformly coated with flux.Type: ApplicationFiled: October 15, 2002Publication date: April 15, 2004Inventors: Mohan R. Nagar, Mukul A. Joshi
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Publication number: 20040070058Abstract: A packaged integrated circuit including a package substrate having electrical contacts for receiving an integrated circuit. The integrated circuit is electrically connected to the electrical contacts of the package substrate. A stiffener is mounted to the package substrate, where the stiffener has a non-orthogonal cut out in which the integrated circuit is disposed. The edges of the cut out are disposed at no greater a distance from the corners of the integrated circuit than they are from the sides of the integrated circuit.Type: ApplicationFiled: October 15, 2002Publication date: April 15, 2004Inventors: Mukul A. Joshi, Mohan R. Nagar, Sarathy Rajagopalan
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Patent number: 6717423Abstract: A probe structure with a connector connecting the probe structure to a time domain reflectometry tester, where the connector has a signal conductor and a ground conductor. A back side layer is connected to the connector. A probe side layer with contacts is sandwiched with the back side layer in a layered substrate. The probe side layer has a centrally disposed signal contact and surrounding ground contacts. A conductive layer is disposed between the back side layer and the probe side layer. The conductive layer is connected to the ground conductor of the connector and to the ground contacts of the probe side layer contacts. A via extends from the back side layer to the probe side layer. The via is connected to the signal conductor of the connector, and is also connected to the centrally disposed signal contact of the probe side layer contacts. The via does not make connection with the conductive layer.Type: GrantFiled: October 9, 2002Date of Patent: April 6, 2004Assignee: LSI Logic CorporationInventors: Aritharan Thurairajaratnam, Mohan R. Nagar
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Patent number: 6605954Abstract: An electrically non conducting material disposed within one or more of the voids of a probe card between a substrate thereof and a tester interface to reinforce the substrate against flexing, bending, and warpage.Type: GrantFiled: January 23, 2002Date of Patent: August 12, 2003Assignee: LSI Logic CorporationInventor: Mohan R. Nagar