Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.

Abstract: The present disclosure provides a method and system for evaluating a machine learning model using an evaluation dataset for the machine learning model. The evaluation dataset includes for each entity in a group of entities: (i) an ordered set of attribute values for the entity, each attribute value corresponding to a respective attribute in a set of attributes that is common for all of the entities in the group of entities, and (ii) an outcome prediction generated for the entity by the machine learning model based on the ordered set of attribute values for the entity, wherein the outcome prediction generated for each entity is either a first outcome or a second outcome. Based on the evaluation dataset, using an optimization process, respective importance values are computed for the attributes, the respective importance values indicating attributes that are most responsible for the machine learning model predicting a first outcome.

Abstract: A transistor includes a semiconductor substrate, a first source/drain region and a second source/drain region in the semiconductor substrate with a channel region between the source/drain regions, and a gate over the channel region. In addition, the transistor includes a first phase transition material (PTM) region between the first source/drain region and the channel region, and a second PTM region between the second source/drain region and the channel region. The PTM regions provide the transistor with improved off-state current (IOFF) without affecting the on-state current (ION), and thus an improved ION/IOFF ratio. The transition threshold of PTM regions from dielectric to conductor can be customized based on, for example, PTM material type, doping therein, and/or strain therein.

Abstract: A transistor includes a semiconductor substrate, a first source/drain region and a second source/drain region in the semiconductor substrate with a channel region between the source/drain regions, and a gate over the channel region. In addition, the transistor includes a first phase transition material (PTM) region between the first source/drain region and the channel region, and a second PTM region between the second source/drain region and the channel region. The PTM regions provide the transistor with improved off-state current (IOFF) without affecting the on-state current (ION), and thus an improved ION/IOFF ratio. The transition threshold of PTM regions from dielectric to conductor can be customized based on, for example, PTM material type, doping therein, and/or strain therein.

Abstract: A method of forming a SRAM semiconductor device with reduced area layout and a resulting device are provided. Embodiments include forming a first field effect transistor (FET) over a substrate; forming an insulating material over the first FET; forming a second FET over the insulating material; and patterning the first FET, insulating material and second FET to form fins over the substrate.

Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

Abstract: A method of forming a SRAM semiconductor device with reduced area layout and a resulting device are provided. Embodiments include forming a first field effect transistor (FET) over a substrate; forming an insulating material over the first FET; forming a second FET over the insulating material; and patterning the first FET, insulating material and second FET to form fins over the substrate.

Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.

Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.

Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.