Patents by Inventor Mohit Parnami

Mohit Parnami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit design synthesis using slack diagrams
    Patent number: 9330216
    Abstract: An updated integrated circuit (IC) design is generated by applying a histogram-based algorithm to an invalid, current IC design. The histogram-based algorithm includes worst negative slack (WNS) optimization followed by total negative slack (TNS) optimization. WNS optimization uses the slack histogram for the current IC design to generate an invalid, but improved, intermediate IC design. TNS optimization uses the slack histogram of the intermediate IC design to generate the updated IC design.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 3, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Mohit Parnami, Sorabh Sachdeva
  • Low leakage flip-flop circuit
    Patent number: 9312834
    Abstract: An integrated circuit having reduced power consumption includes a clock-gating cell, a transistor and a flip-flop. The clock-gating cell receives a dynamic enable signal, generates a latched-enable signal and gates a clock signal provided to the flip-flop. The flip-flop includes first and second latches. The transistor receives an inverted latched-enable signal from the clock-gating cell and switches ON or OFF based on the logic state of the inverted latched-enable signal. The transistor provides a voltage signal to the flip-flop circuit based on the state of the flip-flop in order to control the state of the flip-flop, which reduces power consumption of the integrated circuit.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: April 12, 2016
    Assignee: FREESCALE SEMICONDUCTORS,INC.
    Inventors: Mohit Parnami, Gaurav Goyal
  • IC DESIGN SYNTHESIS USING SLACK DIAGRAMS
    Publication number: 20150379175
    Abstract: An updated integrated circuit (IC) design is generated by applying a histogram-based algorithm to an invalid, current IC design. The histogram-based algorithm includes worst negative slack (WNS) optimization followed by total negative slack (TNS) optimization. WNS optimization uses the slack histogram for the current IC design to generate an invalid, but improved, intermediate IC design. TNS optimization uses the slack histogram of the intermediate IC design to generate the updated IC design.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Mohit Parnami, Sorabh Sachdeva