Patents by Inventor Mojtaba Mehrara
Mojtaba Mehrara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210304264Abstract: The present disclosure relates to the implementation of a pricing structure for the private booking of travel experiences. An experience is offered publicly, so as to be bookable by a plurality of customers, each customer booking a subset of a number of available slots for attendees. A customer may convert the experience from a public experience to a private experience by paying at least a minimum price for the private booking. Where the per person cost would exceed the minimum price, the customer pays an additional per guest value. A plurality of differing pricing rules may be applied in correspondence based on the respective numbers of different types of guests attending the event, or differing date/time instances of the experience.Type: ApplicationFiled: March 25, 2020Publication date: September 30, 2021Applicant: Airbnb, Inc.Inventors: Benjamin Chute, Eric Ertmann, Andrew Hunt, Kristen Jaber, Mojtaba Mehrara, Pauline Nguyen, James Ostrowski, Gabriel Radovsky, Yunshan Weng
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Patent number: 9645802Abstract: A device compiler and linker is configured to group instructions into different strands for execution by different threads based on the dependence of those instructions on other, long-latency instructions. A thread may execute a strand that includes long-latency instructions, and then hardware resources previously allocated for the execution of that thread may be de-allocated from the thread and re-allocated to another thread. The other thread may then execute another strand while the long-latency instructions are in flight. With this approach, the other thread is not required to wait for the long-latency instructions to complete before acquiring hardware resources and initiating execution of the other strand, thereby eliminating at least a portion of the time that the other thread would otherwise spend waiting.Type: GrantFiled: August 7, 2013Date of Patent: May 9, 2017Assignee: NVIDIA CorporationInventors: Mojtaba Mehrara, Michael Garland, Gregory Diamos
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Patent number: 9424038Abstract: A compiler-controlled technique for scheduling threads to execute different regions of a program. A compiler analyzes program code to determine a control flow graph for the program code. The control flow graph contains regions and directed edges between regions. The regions have associated execution priorities. The directed edges indicate the direction of program control flow. Each region has a thread frontier which contains one or more regions. The compiler inserts one or more update predicate mask variable instructions at the end of a region. The compiler also inserts one or more conditional branch instructions at the end of the region. The conditional branch instructions are arranged in order of execution priority of the regions in the thread frontier of the region, to enforce execution priority of the regions at runtime.Type: GrantFiled: December 10, 2012Date of Patent: August 23, 2016Assignee: NVIDIA CorporationInventors: Gregory Diamos, Mojtaba Mehrara
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Patent number: 9329846Abstract: Cooperative program code transformation includes receiving a transformation hint request, obtaining a suitable transformation hint, and providing the suitable transformation hint such that it is used to transform at least a portion of the program code and generate optimized code.Type: GrantFiled: November 22, 2010Date of Patent: May 3, 2016Assignee: Parakinetics Inc.Inventors: David I. August, Kevin C. Fan, Jae Wook Lee, Scott A. Mahlke, Mojtaba Mehrara
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Patent number: 9274792Abstract: A compiler-controlled technique for scheduling threads to execute different regions of a program. A compiler analyzes program code to determine a control flow graph for the program code. The control flow graph contains regions and directed edges between regions. The regions have associated execution priorities. The directed edges indicate the direction of program control flow. Each region has a thread frontier which contains one or more regions. The compiler inserts one or more update predicate mask variable instructions at the end of a region. The compiler also inserts one or more conditional branch instructions at the end of the region. The conditional branch instructions are arranged in order of execution priority of the regions in the thread frontier of the region, to enforce execution priority of the regions at runtime.Type: GrantFiled: December 10, 2012Date of Patent: March 1, 2016Assignee: NVIDIA CorporationInventors: Gregory Diamos, Mojtaba Mehrara
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Patent number: 9229717Abstract: A method for allocating registers within a processing unit. A compiler assigns a plurality of instructions to a plurality of processing clusters. Each instruction is configured to access a first virtual register within a live range. The compiler determines which processing cluster in the plurality of processing clusters is an owner cluster for the first virtual register within the live range. The compiler configures a first instruction included in the plurality of instructions to access a first global virtual register.Type: GrantFiled: December 11, 2012Date of Patent: January 5, 2016Assignee: NVIDIA CorporationInventors: Mojtaba Mehrara, Gregory Diamos
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Publication number: 20150046684Abstract: A device compiler and linker is configured to group instructions into different strands for execution by different threads based on the dependence of those instructions on other, long-latency instructions. A thread may execute a strand that includes long-latency instructions, and then hardware resources previously allocated for the execution of that thread may be de-allocated from the thread and re-allocated to another thread. The other thread may then execute another strand while the long-latency instructions are in flight. With this approach, the other thread is not required to wait for the long-latency instructions to complete before acquiring hardware resources and initiating execution of the other strand, thereby eliminating at least a portion of the time that the other thread would otherwise spend waiting.Type: ApplicationFiled: August 7, 2013Publication date: February 12, 2015Applicant: NVIDIA CORPORATIONInventors: Mojtaba Mehrara, Michael Garland, Gregory Diamos
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Publication number: 20140165049Abstract: A compiler-controlled technique for scheduling threads to execute different regions of a program. A compiler analyzes program code to determine a control flow graph for the program code. The control flow graph contains regions and directed edges between regions. The regions have associated execution priorities. The directed edges indicate the direction of program control flow. Each region has a thread frontier which contains one or more regions. The compiler inserts one or more update predicate mask variable instructions at the end of a region. The compiler also inserts one or more conditional branch instructions at the end of the region. The conditional branch instructions are arranged in order of execution priority of the regions in the thread frontier of the region, to enforce execution priority of the regions at runtime.Type: ApplicationFiled: December 10, 2012Publication date: June 12, 2014Applicant: NVIDIA CORPORATIONInventors: Gregory DIAMOS, Mojtaba MEHRARA
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Publication number: 20140164745Abstract: A method for allocating registers within a processing unit. A compiler assigns a plurality of instructions to a plurality of processing clusters. Each instruction is configured to access a first virtual register within a live range. The compiler determines which processing cluster in the plurality of processing clusters is an owner cluster for the first virtual register within the live range. The compiler configures a first instruction included in the plurality of instructions to access a first global virtual register.Type: ApplicationFiled: December 11, 2012Publication date: June 12, 2014Applicant: NVIDIA CORPORATIONInventors: Mojtaba MEHRARA, Gregory DIAMOS
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Patent number: 7598766Abstract: A fabrication technique called “component and polymorphic network,” in which semiconductor chips are made from small prefabricated bare electronic component dies, e.g., application specific integrated circuits (ASICs), that are assembled according to designer specifications, and bonded to a semiconductor substrate comprising the polymorphic network. The component and polymorphic network assembly has a low overhead for producing custom chips. In another exemplary embodiment, the polymorphic network can be combined with functional components in a single die. The interconnect scheme for ports on the polymorphic network can be configured or reconfigured with configuration data prior to the runtime of an application, to achieve different interconnect schemes.Type: GrantFiled: January 9, 2008Date of Patent: October 6, 2009Assignees: University of Washington, Microsoft Corporation, Regents of the U of MichiganInventors: Martha Mercaldi-Kim, Mark Oskin, John Davis, Todd Austin, Mojtaba Mehrara
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Publication number: 20080164907Abstract: A fabrication technique called “component and polymorphic network,” in which semiconductor chips are made from small prefabricated bare electronic component dies, e.g., application specific integrated circuits (ASICs), that are assembled according to designer specifications, and bonded to a semiconductor substrate comprising the polymorphic network. The component and polymorphic network assembly has a low overhead for producing custom chips. In another exemplary embodiment, the polymorphic network can be combined with functional components in a single die. The interconnect scheme for ports on the polymorphic network can be configured or reconfigured with configuration data prior to the runtime of an application, to achieve different interconnect schemes.Type: ApplicationFiled: January 9, 2008Publication date: July 10, 2008Applicant: University of WashingtonInventors: Martha Mercaldi-Kim, Mark Oskin, John Davis, Todd Austin, Mojtaba Mehrara