Abstract: A structure, a system, and a method for manufacture of crosstalk-free wafer level chip scale packaging (WLCSP) structure for high frequency applications is provided. An illustrative embodiment comprises a substrate on which various layers and structures form circuitry, a signal pin formed on the substrate and coupled with the circuitry, a ground ring encircling the signal pin, and a grounded solder bump coupled to the ground ring.

Abstract: An integrated circuit device with embedded passive component by flip-chip connection is provided which includes a flip chip and a dummy chip. The dummy chip includes at least an embedded passive component, a plurality of redistribution traces and a plurality of flip-chip pads. The flip chip is smaller than the dummy chip and is mounted on a surface of the dummy chip with the flip-chip pads. The embedded passive component is electrically connected to the flip chip via the redistribution traces and the flip-chip pads. A plurality of solder balls are placed at the peripheral region of the surface of the dummy chip.

Abstract: The interconnecting structure for a semiconductor die includes a die having bonding pads on an active surface; a core attached the side wall (edge) of the die by adhesion material; an isolating base adhered on the active surface of the die by adhesion glue; a through silicon via (TSV) open from the back side of the die to expose the bonding pads; a build up layer coupled between the bonding pads to terminal metal pads by the through silicon via; solder balls melted on terminal pads, wherein the terminal pads located on the core and/or the die.

Abstract: A structure, a system, and a method for manufacture of crosstalk-free wafer level chip scale packaging (WLCSP) structure for high frequency applications is provided. An illustrative embodiment comprises a substrate on which various layers and structures form circuitry, a signal pin formed on the substrate and coupled with the circuitry, a ground ring encircling the signal pin, and a grounded solder bump coupled to the ground ring.

Abstract: An integrated circuit device with embedded passive component by flip-chip connection is provided which includes a flip chip and a dummy chip. The dummy chip includes at least an embedded passive component, a plurality of redistribution traces and a plurality of flip-chip pads. The flip chip is smaller than the dummy chip and is mounted on a surface of the dummy chip with the flip-chip pads. The embedded passive component is electrically connected to the flip chip via the redistribution traces and the flip-chip pads. A plurality of solder balls are placed at the peripheral region of the surface of the dummy chip.

Abstract: An integrated circuit device with embedded passive component by flip-chip connection is provided which includes a flip chip and a dummy chip. The dummy chip includes at least an embedded passive component, a plurality of redistribution traces and a plurality of flip-chip pads. The flip chip is smaller than the dummy chip and is mounted on a surface of the dummy chip with the flip-chip pads. The embedded passive component is electrically connected to the flip chip via the redistribution traces and the flip-chip pads. A plurality of solder balls are placed at the peripheral region of the surface of the dummy chip.

Abstract: A test structure for testing a multidirectional current leakage path. A first doped region of a first conductivity is in the first well of the first conductivity in a substrate, in which the first doped region has a dopant concentration higher than the first well has. A first contact is on the first doped region and contacts the first doped region. The first contact has first and second portions respectively parallel to the first and second directions. A plurality of second doped regions of a second conductivity are in the first well and isolated from the first doped region. In a third direction, the second regions are adjacent to each another and isolate the first portion from the second portion. A plurality of second contacts are on the second doped regions and each one is corresponding to each the second doped region. With a relative shift between the first contact and the second doped region, the partial overlap is used in the test of a multidirectional leakage path.

Abstract: A method of enhancing gate lithography performance by polysilicon chemical-mechanical polishing includes depositing a gate polysilicon layer on a semiconductor substrate which has a field oxide isolation structure, and then performing a polysilicon chemical-mechanical polishing after a gate polysilicon layer is deposited in order to smooth the uneven polysilicon surface resulting from the field oxide isolation structure so as to lessen the next lithography process fault because of the non-flatness.

Abstract: A chip structure comprising a substrate, a circuitry unit, a plurality of bonding pads, a first passivation layer and a redistribution layer is provided. The circuitry unit is disposed on the substrate, and the bonding pads are disposed on the circuitry unit. Moreover, the first passivation layer is disposed on the circuitry unit and exposes the bonding pads. The redistribution layer of a Ti/Cu/Ti multi-layered structure is disposed on the first passivation layer, and is electrically connected with the bonding pads. In addition, the redistribution layer of a Ti/Cu/Ti multi-layered structure has excellent conductivity such that electrical characteristics of the chip structure are enhanced effectively.

Abstract: A chip structure and the manufacturing process thereof are provided. The feature of the present application is that the chip structure has a first passivation layer covering a substrate of the chip and exposing each of bonding pads and a portion of the substrate surface, and a second passivation layer covering the sidewalls of the first passivation layer and the portion of substrate surface exposed by the first passivation layer, to prevent moisture infiltration from the edge of the substrate. Therefore, the reliability of the chip structure is enhanced.

Abstract: A method of forming a trench isolation device capable of reducing corner recess comprising forming a pad oxide layer and a silicon nitride mask layer on a semiconductor base, and forming a trench by etching. Next, a liner oxide layer is formed on the semiconductor base and on the surface of the shallow trench. Then, the silicon nitride mask layer will be etched to reveal the corner. Finally, a layer of oxide is formed on the base to fill up the trench so that the trench isolation device can be completed. The present invention is designed to solve the corner recess problem, reduce generation of kick effect, and enhance the device characteristics and electrical quality.

Abstract: A test structure for testing a multidirectional current leakage path. A first doped region of a first conductivity is in the first well of the first conductivity in a substrate, in which the first doped region has a dopant concentration higher than the first well has. A first contact is on the first doped region and contacts the first doped region. The first contact has first and second portions respectively parallel to the first and second directions. A plurality of second doped regions of a second conductivity are in the first well and isolated from the first doped region. In a third direction, the second regions are adjacent to each another and isolate the first portion from the second portion. A plurality of second contacts are on the second doped regions and each one is corresponding to each the second doped region. With a relative shift between the first contact and the second doped region, the partial overlap is used in the test of a multidirectional leakage path.

Abstract: A test key for bridging and continuity testing is provided, comprising at least one test unit, which is composed of a first strand and a second strand embedded or non-touching intertwined with each other. The strand comprising a closed hook, a corresponding extension and a corresponding connection. The corresponding connections are electrically connected to an external voltage by at least one test pad, wherein the closed hook of the first strand is parallel with the closed hook of the second strand. A first corner is formed between the closed hooks and the corresponding extension, causing the closed hook of the first strands to be adjacent and parallel with the closed hook and the extension of the second strand. Moreover, another corner is formed between the extension and the corresponding connection, causing the connection of the first strand to be adjacent and parallel with the extension of second strand, forming an intertwining pattern.

Abstract: A manufacturing method of a semiconductor device for a wire-bonding and flip-chip bonding package mainly comprises the following steps. First, a chip having a plurality of bonding pads and a passivation layer exposing the bonding pads is provided. Next, an under bump metallurgy layer having an aluminum layer, a nickel-vanadium layer and a copper layer is formed on each of the bonding pads. Then, a portion of the copper layer and the nickel-vanadium layer formed over some of the bonding pads is removed so as to leave a portion of the copper layer and the nickel-vanadium layer remained over some of the bonding pads to form patterned copper layers and patterned nickel-vanadium layers. Next, a plurality of solder bumps are formed on the patterned copper layers. Finally, a reflowing process is performed to have the solder bumps secured to the patterned copper layers. In addition, a semiconductor device formed by the manufacturing method is provided.

Abstract: A method for improving the flatness of an oxide layer comprising the steps of providing a semiconductor structure, forming a polysilicon layer on the semiconductor structure, utilizing chemical mechanical polishing to planarize the polysilicon layer, and forming an oxide layer on the polysilicon layer. As a result of using chemical mechanical polishing on the polysilicon layer, an improved flatness of the subsequently formed oxide layer is achieved.

Abstract: An integrated circuit device with embedded passive component by flip-chip connection is provided which includes a flip chip and a dummy chip. The dummy chip includes at least an embedded passive component, a plurality of redistribution traces and a plurality of flip-chip pads. The flip chip is smaller than the dummy chip and is mounted on a surface of the dummy chip with the flip-chip pads. The embedded passive component is electrically connected to the flip chip via the redistribution traces and the flip-chip pads. A plurality of solder balls are placed at the peripheral region of the surface of the dummy chip.