Abstract: A method for fabricating a dual-gate semiconductor device. A preferred embodiment comprises forming a gate stack having a first portion and a second portion, the first portion and the second portion including a different composition of layers, forming photoresist structures on the gate stack to protect the material to be used for the gate structures, etching away a portion of the unprotected material, forming recesses adjacent to at least one of the gate structures in the substrate upon which the gate structures are disposed, and forming a source region and the drained region in the respective recesses. The remaining portions of the gate stack layers that are not a part of a gate structure are then removed. In a particularly preferred embodiment, an oxide is formed on the vertical sides of the gate structures prior to etching to create the source and drain regions.

Abstract: Provided is a method for forming a composite barrier layer with superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer generally form boundaries with dielectric materials and crystalline layers generally form boundaries with conductive materials such as interconnect materials.

Abstract: A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

Abstract: An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.

Abstract: A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.

Abstract: A composite barrier layer provides superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer are generally disposed to form boundaries with dielectric materials and crystalline layers are generally disposed to form boundaries with conductive materials such as interconnect materials.

Abstract: A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual damascene structure is filled with copper. An anneal is applied to the created copper interconnect after which excess copper is removed from the dielectric. Of critical importance to the invention, a thin layer of oxide is then deposited as a cap layer over the copper dual damascene interconnect, an etch stop layer is then deposited over the thin layer of oxide for continued upper-level metallization.

Abstract: A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a contact extending from a top surface of the first ILD into the first ILD; a second ILD over the first ILD; a bottom inter-metal dielectric (IMD) over the second ILD; and a dual damascene structure comprising a metal line in the IMD and a via in the second ILD, wherein the via is connected to the contact.

Abstract: A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.

Abstract: A method for forming a semiconductor structure includes forming a gate dielectric layer over a substrate. A top surface of the gate dielectric layer is treated so as to at least partially nitridize the gate dielectric layer. The treated gate dielectric layer is thermally treated with an oxygen-containing precursor such that the at least partially nitridized gate dielectric layer has a nitrogen concentration between about 0.5 atomic percentage (at. %) and about 20 at %.

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes providing a first chamber and a second chamber. The first chamber and the second chamber are connected by a pressure differential unit, for depositing a metallic film over a substrate in the first chamber, transferring the substrate to the second chamber via the pressure differential unit without exposing the substrate to the ambient environment, and depositing a silicon-containing film on the metallic film in the second chamber.

Abstract: A method for fabricating a dual-gate semiconductor device. A preferred embodiment comprises forming a gate stack having a first portion and a second portion, the first portion and the second portion including a different composition of layers, forming photoresist structures on the gate stack to protect the material to be used for the gate structures, etching away a portion of the unprotected material, forming recesses adjacent to at least one of the gate structures in the substrate upon which the gate structures are disposed, and forming a source region and the drained region in the respective recesses. The remaining portions of the gate stack layers that are not a part of a gate structure are then removed. In a particularly preferred embodiment, an oxide is formed on the vertical sides of the gate structures prior to etching to create the source and drain regions.

Abstract: Generally disclosed is a method of a device comprising forming a polysilicon stack including a first and a second polysilicon layer with an intervening etch stop layer, wherein the first polysilicon layer height is at least one third a height of the polysilicon stack height, removing the second polysilicon layer and the etch stop layer, and reacting the first polysilicon layer with a metal to fully silicide the first polysilicon layer. Fully silicided (FUSI) gates can hence be formed with uniform gate height. The thin first polysilicon layer allows for siliciding with a lower thermal budge and with better uniformity of the silicide concentration throughout the layer.

Abstract: A semiconductor structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a gate dielectric over the first surface of the semiconductor substrate, a gate electrode over the gate dielectric, a source/drain region having at least a portion in the semiconductor substrate, a dielectric layer having a first surface and a second surface opposite the first surface wherein the first surface of the dielectric layer adjoins the second surface of the semiconductor substrate, and a contact plug in the dielectric layer, wherein the contact plug extends from a bottom side of the source/drain region to the second surface of the dielectric layer.

Abstract: A strain-induced layer is formed atop a MOS device in order to increase carrier mobility in the channel region. The dimension of the strain-induced layer in preferred embodiments may lead to an optimized drive current increase and improved drive current uniformity in an NMOS and PMOS device. An advantage of the preferred embodiments is that improved device performance is obtained without adding complex processing steps. A further advantage of the preferred embodiments is that the added processing steps can be readily integrated into a known CMOS process flow. Moreover, the creation of the photo masks defining the tensile and compressive strain-induced layers does not require extra design work on an existed design database.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric on a substrate; introducing metal dopants into the gate dielectric; annealing the gate dielectric; and forming a gate electrode on the gate dielectric.

Abstract: A structure for an integrated circuit is disclosed. The structure includes a crystalline substrate and four crystalline layers. The first crystalline layer of first lattice constant is positioned on the crystalline substrate. The second crystalline layer has a second lattice constant different from the first lattice constant, and is positioned on said first crystalline layer. The third crystalline layer has a third lattice constant different than said second lattice constant, and is positioned on said second crystalline layer. The strained fourth crystalline layer includes, at least partially, a MOSFET device.

Abstract: A SiOC layer and/or a SiC layer of an etch stop layer may be improved by altering the process used to form them. In a bi-layer structure, a SiOC layer and/or a SiC layer may be improved to provide better reliability. A silicon carbide (SiC) layer may be used to form a single-layer etch stop layer, while also acting as a glue layer to improve interface adhesion. Preferably, the SiC layer is formed in a reaction chamber having a flow of substantially pure trimetholsilane (3MS) streamed into and through the reaction chamber under a pressure of less than about 2 torr therein. Preferably, the reaction chamber is energized with high frequency RF power of about 100 watts or more. Preferably, the SiOC layer is formed in a reaction chamber having a flow of 3MS and CO2, and is energized with low frequency RF power of about 100 watts or more.

Abstract: A method of forming a gate dielectric layer includes forming a gate dielectric layer over a substrate. The gate dielectric layer is processed with carbon-containing ions. The gate dielectric layer is thermally processed, thereby providing the gate dielectric layer with a level of carbon between about 1 atomic % and about 20 atomic %.

Abstract: Semiconductor structures having a silicided gate electrode and methods of manufacture are provided. A device comprises a first silicided structure formed in a first active region and a second silicided structure formed in a second active region. The two silicided structures have different metal concentrations. A method of forming a silicided device comprises forming a polysilicon structure on the first and second device fabrication regions. Embodiments include replacing a first portion of the polysilicon structure on the first device fabrication region with a metal and replacing a second portion of the polysilicon structure on the second device fabrication region with the metal. Preferably, the second portion is different than the first portion. Embodiments further include reacting the polysilicon structures on the first and second device fabrication regions with the metal to form a silicide.