Patents by Inventor Monish Shah
Monish Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230214295Abstract: The methods and systems improve uncorrectable error (UE) and silent data corruption (SDC) rates for memory chips and improve error correction of the memory chips. The systems may include a memory bank with a plurality of memory chips in communication with a memory controller. The memory bank may use one additional memory chip that stores a bitwise parity of the data stored in the remaining memory chips of the memory bank. The parity bits are used to rebuild corrupted data when a UE occurs. The parity bits are also used to detect whether a SDC occurred in the data.Type: ApplicationFiled: March 14, 2023Publication date: July 6, 2023Inventor: Monish SHAH
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Patent number: 11640334Abstract: The methods and systems improve uncorrectable error (UE) and silent data corruption (SDC) rates for memory chips and improve error correction of the memory chips. The systems may include a memory bank with a plurality of memory chips in communication with a memory controller. The memory bank may use one additional memory chip that stores a bitwise parity of the data stored in the remaining memory chips of the memory bank. The parity bits are used to rebuild corrupted data when a UE occurs. The parity bits are also used to detect whether a SDC occurred in the data.Type: GrantFiled: May 21, 2021Date of Patent: May 2, 2023Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventor: Monish Shah
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Publication number: 20220374307Abstract: The methods and systems improve uncorrectable error (UE) and silent data corruption (SDC) rates for memory chips and improve error correction of the memory chips. The systems may include a memory bank with a plurality of memory chips in communication with a memory controller. The memory bank may use one additional memory chip that stores a bitwise parity of the data stored in the remaining memory chips of the memory bank. The parity bits are used to rebuild corrupted data when a UE occurs. The parity bits are also used to detect whether a SDC occurred in the data.Type: ApplicationFiled: May 21, 2021Publication date: November 24, 2022Inventor: Monish SHAH
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Publication number: 20220308960Abstract: Data redundancy arrangements for memory and storage devices are discussed herein. In one example, a method of operating a data storage system includes writing data to a non-volatile memory die by at least spanning bits of the data and one or more data redundancy bits generated for the data across a quantity of data storage cells of more than one plane of the non-volatile memory die. The more than one plane of the non-volatile memory die comprise groupings of data storage cells having independent source lines and bit lines that provide for concurrent write operations to the more than one plane.Type: ApplicationFiled: June 13, 2022Publication date: September 29, 2022Inventors: Chenfeng ZHANG, Vamsi SATA, Monish SHAH
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Patent number: 11422886Abstract: Data redundancy arrangements for memory and storage devices are discussed herein. In one example, a method of operating a data storage system includes identifying a data page for storage in a non-volatile memory die, and generating one or more data redundancy bits for the data page. The method also includes writing the data page to the non-volatile memory die by at least spanning bits of the data page and the one or more data redundancy bits across a quantity of data storage cells that share a structural property in the non-volatile memory die.Type: GrantFiled: January 9, 2020Date of Patent: August 23, 2022Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Chenfeng Zhang, Vamsi Sata, Monish Shah
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Publication number: 20210216399Abstract: Data redundancy arrangements for memory and storage devices are discussed herein. In one example, a method of operating a data storage system includes identifying a data page for storage in a non-volatile memory die, and generating one or more data redundancy bits for the data page. The method also includes writing the data page to the non-volatile memory die by at least spanning bits of the data page and the one or more data redundancy bits across a quantity of data storage cells that share a structural property in the non-volatile memory die.Type: ApplicationFiled: January 9, 2020Publication date: July 15, 2021Inventors: Chenfeng Zhang, Vamsi Sata, Monish Shah
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Patent number: 10942849Abstract: An apparatus includes a host device and a data storage device. The host device is configured to store a first translation map for converting a logical sector to a logical erase unit. The data storage device includes a plurality of flash memory devices and a memory controller operationally coupled with the flash memory devices, each of the flash memory devices being arranged into a plurality of erase units, each of the erase units having a plurality of pages for storing data. The memory controller is configured to receive a second translation map from the host device, the second translation map for converting a logical erase unit to a physical erase unit within the flash memory devices, and store the second translation map in a memory module on the data storage device.Type: GrantFiled: November 18, 2019Date of Patent: March 9, 2021Assignee: Google LLCInventors: Christopher John Sabol, Slava Pestov, Thomas Wyatt Craig, Manuel Enrique Benitez, Monish Shah, Daniel Ari Ehrenberg
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Patent number: 10866755Abstract: IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.Type: GrantFiled: April 2, 2019Date of Patent: December 15, 2020Assignee: Google LLCInventors: Monish Shah, Benjamin Charles Serebrin, Albert Borchers
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Patent number: 10606484Abstract: At least one aspect is directed to a NAND flash storage device including a plurality of NAND flash chips and a controller. The controller is configured to receive data over an input/output (I/O) bus and write the received data to a first NAND flash chip of the plurality of NAND flash chips and a second NAND flash chip of the plurality of NAND flash chips. The write operations to each NAND flash chip do not overlap in time. The controller is configured to read data from whichever of the first NAND flash chip or the second NAND flash chip is not currently executing a write operation such that read operations are not queued behind write operations.Type: GrantFiled: November 17, 2017Date of Patent: March 31, 2020Assignee: Google LLCInventor: Monish Shah
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Publication number: 20200089606Abstract: An apparatus includes a host device and a data storage device. The host device is configured to store a first translation map for converting a logical sector to a logical erase unit. The data storage device includes a plurality of flash memory devices and a memory controller operationally coupled with the flash memory devices, each of the flash memory devices being arranged into a plurality of erase units, each of the erase units having a plurality of pages for storing data. The memory controller is configured to receive a second translation map from the host device, the second translation map for converting a logical erase unit to a physical erase unit within the flash memory devices, and store the second translation map in a memory module on the data storage device.Type: ApplicationFiled: November 18, 2019Publication date: March 19, 2020Inventors: Christopher John Sabol, Slava Pestov, Thomas Wyatt Craig, Manuel Enrique Benitez, Monish Shah, Daniel Ari Ehrenberg
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Patent number: 10482009Abstract: An apparatus includes a host device and a data storage device. The host device is configured to store a first translation map for converting a logical sector to a logical erase unit. The data storage device includes a plurality of flash memory devices and a memory controller operationally coupled with the flash memory devices, each of the flash memory devices being arranged into a plurality of erase units, each of the erase units having a plurality of pages for storing data. The memory controller is configured to receive a second translation map from the host device, the second translation map for converting a logical erase unit to a physical erase unit within the flash memory devices, and store the second translation map in a memory module on the data storage device.Type: GrantFiled: March 15, 2013Date of Patent: November 19, 2019Assignee: GOOGLE LLCInventors: Christopher John Sabol, Slava Pestov, Thomas W. Craig, Manuel Enrique Benitez, Monish Shah, Daniel A. Ehrenberg
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Patent number: 10459847Abstract: A method includes deploying non-volatile random access memory (NVRAM) coupled to a processor or central processing unit (CPU) core of a computing device as a peripheral device via an input/output (I/O) bus, and providing a NVRAM application programming interface (API) for the CPU core to conduct NVRAM read and write operations. Providing the NVRAM API includes allocating a single memory buffer per command to hold data transferred to or from the NVRAM. The method includes configuring the processor in conjunction with the NVRAM API to set up command queues inside in the host Memory Mapped Input Output (MMIO) space.Type: GrantFiled: July 1, 2015Date of Patent: October 29, 2019Assignee: GOOGLE LLCInventors: Monish Shah, Albert Thomas Borchers, Joel Dylan Coburn, Benjamin Charles Serebrin
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Publication number: 20190227729Abstract: IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.Type: ApplicationFiled: April 2, 2019Publication date: July 25, 2019Inventors: Monish Shah, Benjamin Charles Serebrin, Albert Borchers
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Patent number: 10296256Abstract: IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.Type: GrantFiled: September 16, 2016Date of Patent: May 21, 2019Assignee: Google LLCInventors: Monish Shah, Benjamin Charles Serebrin, Albert Borchers
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Publication number: 20180373440Abstract: At least one aspect is directed to a NAND flash storage device including a plurality of NAND flash chips and a controller. The controller is configured to receive data over an input/output (I/O) bus and write the received data to a first NAND flash chip of the plurality of NAND flash chips and a second NAND flash chip of the plurality of NAND flash chips. The write operations to each NAND flash chip do not overlap in time. The controller is configured to read data from whichever of the first NAND flash chip or the second NAND flash chip is not currently executing a write operation such that read operations are not queued behind write operations.Type: ApplicationFiled: November 17, 2017Publication date: December 27, 2018Inventor: Monish Shah
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Publication number: 20180203797Abstract: Compression and decompression of data at high speed in solid state storage is described, including accessing a compressed data comprising a plurality of blocks of the compressed data, decompressing each of the plurality of blocks in a first stage of decompression to produce a plurality of partially decompressed blocks, and reconstructing an original data from the partially decompressed blocks in a second stage of decompression.Type: ApplicationFiled: March 5, 2018Publication date: July 19, 2018Applicant: CNEX Labs, Inc.Inventor: Monish Shah
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Patent number: 9940230Abstract: Compression and decompression of data at high speed in solid state storage is described, including accessing a compressed data comprising a plurality of blocks of the compressed data, decompressing each of the plurality of blocks in a first stage of decompression to produce a plurality of partially decompressed blocks, and reconstructing an original data from the partially decompressed blocks in a second stage of decompression.Type: GrantFiled: October 20, 2011Date of Patent: April 10, 2018Assignee: CNEX Labs, Inc.Inventor: Monish Shah
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Patent number: 9880778Abstract: A memory device includes a plurality of NAND flash chips, a dynamic random access memory (DRAM) portion in data communication with the NAND flash chips, and a controller. Each NAND flash chip has a first storage capacity, and includes a memory section, each memory section including a plurality of pages. The DRAM portion has a second storage capacity that is at least as large as the first storage capacity. The controller is configured to select one of the NAND flash chips as a currently selected NAND flash chip for writing data, copy all valid pages in the currently selected NAND flash chip into the DRAM portion, and, in response to a write request to a logical memory location mapped to a particular physical location in one of the NAND flash chips, allocate the currently selected NAND flash chip for writing to a particular page that includes the particular physical location.Type: GrantFiled: November 9, 2015Date of Patent: January 30, 2018Assignee: Google Inc.Inventor: Monish Shah
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Publication number: 20180018123Abstract: IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.Type: ApplicationFiled: September 16, 2016Publication date: January 18, 2018Inventors: Monish Shah, Benjamin Charles Serebrin, Albert Borchers
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Publication number: 20170131908Abstract: A memory device includes a plurality of NAND flash chips, a dynamic random access memory (DRAM) portion in data communication with the NAND flash chips, and a controller. Each NAND flash chip has a first storage capacity, and includes a memory section, each memory section including a plurality of pages. The DRAM portion has a second storage capacity that is at least as large as the first storage capacity. The controller is configured to select one of the NAND flash chips as a currently selected NAND flash chip for writing data, copy all valid pages in the currently selected NAND flash chip into the DRAM portion, and, in response to a write request to a logical memory location mapped to a particular physical location in one of the NAND flash chips, allocate the currently selected NAND flash chip for writing to a particular page that includes the particular physical location.Type: ApplicationFiled: November 9, 2015Publication date: May 11, 2017Inventor: Monish Shah