Abstract: Disclosed is a method and apparatus for transmitting an object which includes packets and is significant for an application of a receiver, the method including calculating a network latency between a sender and a receiver through a control message for transmitting a plurality of packets constituting the object, detecting that a specific packet is lost among the plurality of packets, calculating a retransmission required time required for retransmitting the specific packet, comparing the retransmission required time with a deadline, and transmitting a NACK message including information related to retransmission of the specific packet to the sender when the retransmission required time is within the deadline, wherein the network latency is used for calculating the deadline determined by latency times for transmission of the object.

Abstract: A hydrogen supply method includes a two-side heat exchange mode in which both introducing a second fluid into a hydrogen storage part after the second fluid exchanges heat with a first fluid in a second heat exchanger in a state in which a compressor is driven to compress the first fluid and introducing the second fluid into the hydrogen storage part after the second fluid is heated or cooled in a thermal device are performed. The method also includes a one-side heat exchange mode in which one of introducing the second fluid into the hydrogen storage part after the second fluid exchanges heat with the first fluid in the second heat exchanger in a state in which the compressor is driven to compress the first fluid and introducing the second fluid into the hydrogen storage part after the second fluid is heated or cooled in the thermal device is performed.

Abstract: A hydrogen storage system is disclosed and includes a storage unit including a plurality of unit storage containers, in which metal hydride materials are respectively provided in an interior thereof and which are connected to each other in parallel, and a thermal fluid line defining a thermal fluid passage, which passes via the plurality of unit storage containers continuously and through which a thermal fluid flows for heating or cooling the unit storage containers, thereby enhancing a storage performance and an efficiency of the hydrogen.

Abstract: A hydrogen storage device includes a storage container having an accommodation space in an interior thereof, a first metal hydride material provided in the interior of the storage container and that stores hydrogen, and a second metal hydride material provided in the interior of the storage container and that stores the hydrogen at a pressure that is different from that of the first metal hydride material. An advantageous effect of restraining an excessive rise of a pressure of the storage container and enhancing safety and reliability may be obtained.

Abstract: A semiconductor device includes a memory core circuit configured to generate core data from bank data outputted by a bank or generate the core data from a dummy column address based on a read operation for the bank. The semiconductor device also includes a data control circuit configured to generate a switching signal from a bank active signal or a dummy bank address based on the read operation for the bank and and configured to control the output of the core data based on the switching signal.

Abstract: An integrated circuit includes an operation control circuit configured to control generation of a sharing signal, a pre-charge signal, a sensing signal, a latch signal, and a calibration enable signal for a calibration operation and a sense amplifying operation. The integrated circuit also includes a signal line sense amplifying circuit configured to receive the sharing signal, the pre-charge signal, the sensing signal, the latch signal, and the calibration enable signal to perform the calibration operation and the sense amplifying operation.

Abstract: A pipe register control signal generation circuit includes a sense amplifier configured to drive a global input/output line according to a result of sensing a voltage difference between a pair of local input/output lines according to a sense amplifier enable signal. The pipe register control signal generation circuit also includes a duplicate sense amplifier configured to simulate the sense amplifier and configured to generate a pipe register control signal according to a result of sensing a difference between a first voltage and a second voltage according to the sense amplifier enable signal.

Abstract: A semiconductor device includes a strobe transmission circuit configured to output an oscillation strobe signal, through a first delay path circuit, as a strobe signal when a first measurement operation is performed and configured to output the oscillation strobe signal through a second delay path circuit as the strobe signal when a second measurement operation is performed, and a calibration circuit configured to compare the number of times the strobe signal toggles during the first measurement operation to the number of times the strobe signal toggles during the second measurement operation to calibrate the delay amounts of the first and second delay path circuits to be the same.

Abstract: A semiconductor device includes a memory core circuit configured to generate core data from bank data outputted by a bank or generate the core data from a dummy column address based on a read operation for the bank. The semiconductor device also includes a data control circuit configured to generate a switching signal from a bank active signal or a dummy bank address based on the read operation for the bank and and configured to control the output of the core data based on the switching signal.

Abstract: A clock signal processing circuit includes a clock buffer configured to generate a pair of second clock signals with opposite phases after receiving a pair of first clock signals with opposite phases and configured to fix the second clock signals to determined levels according to a control signal until toggling of the first clock signals begins.

Abstract: The present disclosure provides an apparatus for setting a gain of a RF repeater includes: a synchronization signal power calculator configured to determine an average received power level of a synchronization signal received over a predetermined number of times as a synchronization signal power; a downlink power calculator configured to calculate a downlink input power according to a power ratio of synchronization signal to data channel signal based on the synchronization signal power; and a downlink gain setting unit configured to calculate a downlink gain by subtracting the downlink input power from a downlink output power determined by hardware specifications to set the downlink gain.

Abstract: A phase correction circuit includes: a test clock generation unit including a plurality of signal paths and configurable to generate a plurality of test clock signals in response to a plurality of selection signals and a plurality of phase control signals; a detection unit configured to generate a plurality of detection voltages using the plurality of test clock signals; and a control unit configured to generate the plurality of selection signals, detect phase skews of the plurality of signal paths according to the plurality of detection voltages, and generate the plurality of phase control signals for correcting the phase skews.

Abstract: A semiconductor apparatus receives a first clock signal and a second clock signal. The semiconductor apparatus configured to perform a training operation internally, the training operation being an operation of internally correcting a phase difference between the first clock signal and the second clock signal by dividing the first clock signal to generate multi-phase signals, detecting phase difference between the second clock signal and the multi-phase signals, and adjusting phases of the multi-phase signals according to a result of the detecting of the phase difference.

Abstract: A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.

Abstract: A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.

Abstract: A clock signal processing circuit includes a clock buffer configured to generate a pair of second clock signals with opposite phases after receiving a pair of first clock signals with opposite phases and configured to fix the second clock signals to determined levels according to a control signal until toggling of the first clock signals begins.

Abstract: A phase correction circuit includes: a test clock generation unit including a plurality of signal paths and configurable to generate a plurality of test clock signals in response to a plurality of selection signals and a plurality of phase control signals; a detection unit configured to generate a plurality of detection voltages using the plurality of test clock signals; and a control unit configured to generate the plurality of selection signals, detect phase skews of the plurality of signal paths according to the plurality of detection voltages, and generate the plurality of phase control signals for correcting the phase skews.

Abstract: A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.

Abstract: A clock compensation circuit includes a delay circuit configured to generate a plurality of second clock signals by delaying a plurality of first clock signals, a voltage conversion circuit configured to convert phase differences between the plurality of second clock signals into voltages and output converted voltages as a plurality of phase difference voltages, and a comparison circuit configured to generate a plurality of phase difference detection signals by comparing the plurality of phase difference voltages with a reference voltage. The clock compensation circuit also includes a phase error control circuit configured to generate a plurality of control signals for controlling the delay circuit, the voltage conversion circuit, and the comparison circuit according to any of the plurality of second clock signals and the plurality of phase difference detection signals.

Abstract: A semiconductor apparatus receives a first clock signal and a second clock signal. The semiconductor apparatus configured to perform a training operation internally, the training operation being an operation of internally correcting a phase difference between the first clock signal and the second clock signal by dividing the first clock signal to generate multi-phase signals, detecting phase difference between the second clock signal and the multi-phase signals, and adjusting phases of the multi-phase signals according to a result of the detecting of the phase difference.