Abstract: Embodiments of the present disclosure relate to a system and an operating method of the system. Based on some embodiments of the disclosed technology, the system may include a random access memory structured to include memory cells to store data, a cache memory configured to cache at least part of the data, and a processor in communication with the random access memory and the cache memory to access at least part of the data from the random access memory or cache memory. The system may determine a cache hit ratio for the cache memory, and may set an operating frequency of the random access memory based on the cache hit ratio.

Abstract: A positive electrode active material including a first lithium composite oxide particle including a secondary particle formed by aggregation of one or more primary particles, and a coating oxide occupying at least a part of at least one of surfaces of the secondary particle, grain boundaries between the primary particles, or surfaces of the primary particles, the positive electrode active material satisfying an equation of 1.3?a/b?3.0, wherein a represents a max peak intensity at 2theta=44.75° to 44.80° and b represents a max peak intensity at 2theta=45.3° to 45.6° in X-ray diffraction (XRD) analysis using Cu K? radiation.

Abstract: Provided are a barium titanate powder having spherical shape fine particles which have an average particle diameter (D50) in a range of about 140-270 nm, a tetragonal structure having a markedly improved tetragonality (c/a) in a range of 1.007-1.01 in contrast to the conventional composition, and at the same time, a markedly improved crystallinity in a range of 93-96%, thereby showing improved dielectric properties, and a manufacturing method thereof.

Abstract: A memory system may include: a memory device configured to store first training information and second training information representing different training patterns; and a memory controller configured to: perform a first training operation on the memory device based on the first training information, and perform, when a result of the first training operation is out of a predetermined range, a second training operation on the memory device plural times based on the second training information.

Abstract: Embodiments of the present disclosure relate to a system and an operating method of the system. Based on some embodiments of the disclosed technology, the system may include a random access memory structured to include memory cells to store data, a cache memory configured to cache at least part of the data, and a processor in communication with the random access memory and the cache memory to access at least part of the data from the random access memory or cache memory. The system may determine a cache hit ratio for the cache memory, and may set an operating frequency of the random access memory based on the cache hit ratio.

Abstract: The present technology relates to an electronic device. According to the present technology, a memory controller may include a training controller, a training data storage, and a machine learning processor. The training controller may perform training of correcting interface signals exchanged with a memory device, generate training data that is a result of the training, and output the training data as sample training data based on a comparison result of a training reference and the training data. The training data storage may store training history information including plural pieces of sample training data. The machine learning processor may update the training reference through machine learning based on the training history information.

Abstract: Embodiments of the present disclosure relate to a system and an operating method of the system. Based on some embodiments of the disclosed technology, the system may include a random access memory structured to include memory cells to store data, a cache memory configured to cache at least part of the data, and a processor in communication with the random access memory and the cache memory to access at least part of the data from the random access memory or cache memory. The system may determine a cache hit ratio for the cache memory, and may set an operating frequency of the random access memory based on the cache hit ratio.

Abstract: A brake caliper assembly may include a caliper body; and a styling cover which is assembled to a seat portion of the caliper body, wherein the styling cover has a mounting rib which is fastened in a state of being inserted into and in contact with an opening portion formed in the seat portion.

Abstract: A brake caliper assembly may include a caliper body; and a styling cover which is assembled to a seat portion of the caliper body, wherein the styling cover has a mounting rib which is fastened in a state of being inserted into and in contact with an opening portion formed in the seat portion.

Abstract: A terminal may be provided that includes: a touch screen; a processor; and a controller. When a touch is input to the touch screen, the processor detects a position of the touch and a magnitude of a pressure of the touch and transfers information on the touch position and information on the magnitude of the touch pressure to the controller. Based on the magnitude of the touch pressure, the controller changes an image which is displayed on a change target region around the touch position, and displays the changed image on the touch screen. The change target region includes a first region and a second region disposed within the first region, an image enlarged perpendicularly to the boundary of the first region is displayed on the first region, and an image reduced perpendicularly to the boundary of the second region is displayed on the second region.