Patents by Inventor MOON-KI JUNG

MOON-KI JUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10839929
    Abstract: A memory device includes a memory cell array including a plurality of memory cells and a memory controller to control the plurality of memory cells. The memory cell array has a first fuse region including a plurality of first fuse cells having a same structure as the plurality of memory cells and a second fuse region including a plurality of second fuse cells having a structure different from a structure of the plurality of memory cells. The memory controller has a fuse selection circuit selecting one of the first fuse region and the second fuse region.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: November 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon Ki Jung, Boh Chang Kim
  • Publication number: 20200160927
    Abstract: A memory device includes a memory cell array including a plurality of memory cells and a memory controller to control the plurality of memory cells. The memory cell array has a first fuse region including a plurality of first fuse cells having a same structure as the plurality of memory cells and a second fuse region including a plurality of second fuse cells having a structure different from a structure of the plurality of memory cells. The memory controller has a fuse selection circuit selecting one of the first fuse region and the second fuse region.
    Type: Application
    Filed: June 19, 2019
    Publication date: May 21, 2020
    Inventors: Moon Ki JUNG, Boh Chang KIM
  • Patent number: 9443582
    Abstract: A method for testing a nonvolatile memory device includes: monitoring a first resistance dispersion and a second resistance dispersion of a nonvolatile memory device, determining a lower test bias level and an upper test bias level that are disposed on opposite sides of a reference bias level, calculating the number of first fail bits generated in the first resistance dispersion based on the lower test bias level and the number of second fail bits generated in the second resistance dispersion based on the upper test bias level, determining a selected reference bias level using the number of the first fail bits and the number of the second fail bits, and trimming the reference bias level to the selected bias level.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: September 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-Ki Jung, Ki-Won Lim
  • Publication number: 20150124515
    Abstract: A method for testing a nonvolatile memory device includes: monitoring a first resistance dispersion and a second resistance dispersion of a nonvolatile memory device, determining a lower test bias level and an upper test bias level that are disposed on opposite sides of a reference bias level, calculating the number of first fail bits generated in the first resistance dispersion based on the lower test bias level and the number of second fail bits generated in the second resistance dispersion based on the upper test bias level, determining a selected reference bias level using the number of the first fail bits and the number of the second fail bits, and trimming the reference bias level to the selected bias level.
    Type: Application
    Filed: August 19, 2014
    Publication date: May 7, 2015
    Inventors: MOON-KI JUNG, KI-WON LIM