Abstract: An example of an apparatus may include NAND memory and circuitry coupled to the NAND memory to monitor a sense voltage for an operation associated with a wordline of the NAND memory, and adjust a negative charge pump for the wordline prior to completion of the operation based on the monitored sense voltage. Other examples are disclosed and claimed.

Abstract: An example of an apparatus may include NAND memory and circuitry coupled to the NAND memory to control access to the NAND memory as two or more groups of memory cells, provide independent operations for the two or more groups of memory cells, share a voltage regulator among at least two of the two or more groups of memory cells, and provide a target constant voltage from the shared voltage regulator to a target group of the two or more groups of memory cells in an independent operation for the target group. Other examples are disclosed and claimed.

Abstract: Described is an apparatus which comprises: a first feedback loop to generate a control signal for regulating an output voltage provided to a load; and a second feedback loop, separate from the first feedback loop, to receive the control signal from the first feedback loop, the second feedback loop to regulate the output voltage provided to the load.

Abstract: Described is an apparatus which comprises: a first feedback loop to generate a control signal for regulating an output voltage provided to a load; and a second feedback loop, separate from the first feedback loop, to receive the control signal from the first feedback loop, the second feedback loop to regulate the output voltage provided to the load.

Abstract: Embodiments include systems, methods, and apparatuses for reading a data signal from a memory, such as a dynamic random access memory (DRAM). In one embodiment, a memory receiver may include a differential amplifier to receive a data signal from the memory and pass a differential output signal based on a voltage difference between the data signal and a reference voltage. The data signal may have a first direct current (DC) average voltage level, and the differential amplifier may shift the differential output signal to a second DC average voltage level that is substantially constant over a range of values of the first DC average voltage level. In another embodiment, a voltage offset compensation (VOC) circuit may apply a compensation voltage to the output signal that is based on an activated rank or an identity of the memory module. Other embodiments may be described and claimed.

Abstract: Embodiments include systems, methods, and apparatuses for reading a data signal from a memory, such as a dynamic random access memory (DRAM). In one embodiment, a memory receiver may include a differential amplifier to receive a data signal from the memory and pass a differential output signal based on a voltage difference between the data signal and a reference voltage. The data signal may have a first direct current (DC) average voltage level, and the differential amplifier may shift the differential output signal to a second DC average voltage level that is substantially constant over a range of values of the first DC average voltage level. In another embodiment, a voltage offset compensation (VOC) circuit may apply a compensation voltage to the output signal that is based on an activated rank or an identity of the memory module. Other embodiments may be described and claimed.

Abstract: Disclosed herein are duty cycle adjustment circuits to control the duty cycle in a clock signal. In some embodiments, a circuit is provided comprising a clock driver to drive a differential clock signal through a clock path. A feedback circuit is coupled (i) to the clock path to monitor offset in the clock signal, and (ii) to the clock driver to digitally control the clock driver offset based on the monitored clock signal offset. Other embodiments are disclosed herein.