Abstract: Various embodiments of the present invention relate to systems and methods for monitoring and tuning detector and modulator resonators during operation. Aspects of the present invention use DC balanced coding of data in optical signals tune and monitor the performance of a resonator. Whether the resonator is being used as a modulator or a detector, the intensity of the light coupled into the resonator is DC balanced and varies as a function of the data being transmitted. Average intensity variations of the light scattered from the resonator are converted into an electronic feedback signal, which is used to determine appropriate levels of thermal and electronic tuning applied to the resonator.

Abstract: Various embodiments of the present invention are directed to stacked memory modules. In one embodiment of the present invention, a memory module comprises at least one memory-controller layer stacked with at least one memory layer. Fine pitched through vias (e.g., through silicon vias) extend approximately perpendicular to a surface of the at least one memory controller through the stack providing electronic communication between the at least one memory controller and the at least one memory layers. Additionally, the memory-controller layer includes at least one external interface configured to transmit data to and from the memory module. Furthermore, the memory module can include an optical layer. The optical layer can be included in the stack and has a bus waveguide to transmit data to and from the at least one memory controller. The external interface can be an optical external interface which interfaces with the optical layer.

Abstract: A synchronous optical bus system for communication between computer system components is described. In one example, the optical bus system is used for communication between a memory controller and memory devices optically coupled to an optical interconnect. Optical bus interface units couple the components to the optical interconnect and are arranged on the optical interconnect in order that a sum of an optical path length from a controller component to each computer system component and from each computer system component to the controller component is the same for all the coupled computer system components. A synchronous protocol is used for communication between the components.

Abstract: A computer network (1) comprises:—at least two processing nodes each having a processor (4) on which one or more user processes are executed and a respective network interface (2); and a switching network (3) which operatively connects the at least two processing nodes together, each network interface (2) including a command processor and a memory wherein the command processor of said network interface (2) is configured to allocate exclusively to a user process being executed on the processor (4) with which the network interface (2) is associated one or more segments of addressable memory in said network interface memory as a respective one or more command queues The network interface (2) is capable of processing command data at high rates and with low latencies whilst maintaining the security of individual user processes.

Abstract: A computer network (1) comprises:- a plurality of processing nodes, at least two of which each having respective addressable memories and respective network interfaces (2); and a switching network (3) which operatively connects the plurality of processing nodes together, each network interface (2) including a memory management unit (8a) having associated with it a memory in which is stored (a) at least one mapping table for mapping 64 bit virtual addresses to the physical addresses of the addressable memory of the respective processing node; and (b) instructions for applying a compression algorithm to said virtual addresses, the at least one mapping table comprising a plurality of virtual addresses and their associated physical addresses ordered with respect to compressed versions of the 64 bit virtual addresses. The network interface (2) provides visibility across the network of areas of the memory of individual processing nodes in a way which supports full scalability of the network.