Abstract: Two or more erase sectors (blocks) in a given physical sector of the array. When (after) erasing a target block, determining whether a neighbor block needs to be refreshed by checking a sub-population of Vt distributions at a given program level. Various timings and strategies for performing the refresh operation are disclosed. The effects of word line disturb (gate disturb) may thereby be reduced.

Abstract: A system and a method for operating a non-volatile memory (NVM) device including a micro-controller adapted to control peripheral circuitry associated with an NVM array. The method includes providing at least one operation command to the micro-controller of the NVM device and applying operating signals to peripheral circuitry of the NVM device to operate the NVM array based on at least one operation command. The system includes: (1) a NVM device with a NVM array adapted to store data and commands, peripheral circuitry adapted to operate the NVM array and a micro-controller adapted to control the peripheral circuitry; and (2) an external device to provide at least one command to the micro-controller of the NVM device.

Abstract: A method for programming in parallel reference cells to be used for operating other cells of a memory cell array, the method including: a) reading each of the reference cells of a memory cell array with a sense amplifier, the sense amplifier providing an output indicative of a programmed state of the reference cell relative to another bit in the array, b) reading each of the reference cells of a memory cell array with a sense amplifier while using read conditions to determine if the reference cells have reached a target level, c) determining if a programming pulse should be applied to the reference cell by comparing the output of the sense amplifier to a predefined target “0” or “1”, d) setting a buffer bit, corresponding to the output of the sense amplifier, in a sticky bit buffer to a first logical state if the reference cell needs to be programmed, and not changing a logical state of the buffer bit if the reference cell does not need to be programmed, e) performing steps a)-d) for a desired address range i

Abstract: A system and a method for operating a non-volatile memory (NVM) device including a micro-controller adapted to control peripheral circuitry associated with an NVM array. The method includes providing at least one operation command to the micro-controller of the NVM device and applying operating signals to peripheral circuitry of the NVM device to operate the NVM array based on at least one operation command. The system includes: (1) a NVM device with a NVM array adapted to store data and commands, peripheral circuitry adapted to operate the NVM array and a micro-controller adapted to control the peripheral circuitry; and (2) an external device to provide at least one command to the micro-controller of the NVM device.

Abstract: A method for operating a memory cell array, the method comprising assigning word lines of a memory cell array as addresses for writing sets of data thereto from a cache memory, and scrambling addresses of the sets of data by writing a first chunk of the particular set of data from the cache memory to a first word line of the array, and writing a second chunk of the particular set of data from the cache memory to a second word line of the array, the first chunk comprising a first subset of the particular set of data and the second chunk comprising a second subset of the particular set of data.

Abstract: A method for operating a memory cell array, the method comprising assigning word lines of a memory cell array as addresses for writing sets of data thereto from a cache memory, and scrambling addresses of the sets of data by writing a first chunk of the particular set of data from the cache memory to a first word line of the array, and writing a second chunk of the particular set of data from the cache memory to a second word line of the array, the first chunk comprising a first subset of the particular set of data and the second chunk comprising a second subset of the particular set of data.

Abstract: Disclosed is a method utilizing dynamic masking for efficiently programming an N-bit memory array and, more generally, for mapping successive subsets of data segments into a succession of N-bit auxiliary bytes. When the number of programming bits in an incoming byte exceeds K, a mask maps the bit pattern of the incoming byte into sequential N-bit auxiliary bytes. A first auxiliary byte retains the bit pattern of the incoming byte up to the Kth programming bit, and the remaining bit positions of the first auxiliary byte exhibit a state complementary to the programming bits. A second auxiliary byte retains the bit pattern of the incoming byte starting with the first location after the Kth programming bit and continuing up to the Kth additional programming bit (if any); all remaining bit positions of the second auxiliary byte (including the bit positions that contained programming bits in the first auxiliary byte) exhibit the complementary state.

Abstract: Disclosed is a method utilizing dynamic masking for efficiently programming an N-bit memory array and, more generally, for mapping successive subsets of data segments into a succession of N-bit auxiliary bytes. When the number of programming bits in an incoming byte exceeds K, a mask maps the bit pattern of the incoming byte into sequential N-bit auxiliary bytes. A first auxiliary byte retains the bit pattern of the incoming byte up to the Kth programming bit, and the remaining bit positions of the first auxiliary byte exhibit a state complementary to the programming bits. A second auxiliary byte retains the bit pattern of the incoming byte starting with the first location after the Kth programming bit and continuing up to the Kth additional programming bit (if any); all remaining bit positions of the second auxiliary byte (including the bit positions that contained programming bits in the first auxiliary byte) exhibit the complementary state.