Patents by Inventor Moritaka Iyoda

Moritaka Iyoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8289075
    Abstract: A class-D amplifier for generating from an input signal a digital signal for driving a load, includes an output limit instruction generating section that detects that the digital signal falls outside a limit range and that outputs an output limit instruction signal, an attenuation instruction pulse generating section that includes an integrator for integrating the output limit instruction signal and that outputs a periodical attenuation instruction pulse having pulse width corresponding to an integrated value in the integrator, an attenuating section provided in an input path for the input signal and that attenuates the input signal based on the attenuation instruction pulse, and a mute control section that controls the integrated value in the integrator independently of the output limit instruction signal to control an amount of the attenuation of the attenuating section applied to the input signal.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: October 16, 2012
    Assignee: Yamaha Corporation
    Inventors: Tatsuya Kishii, Moritaka Iyoda, Hirotoshi Tsuchiya, Toshio Maejima, Masayoshi Nakamura, Masato Miyazaki, Akihisa Himeno
  • Publication number: 20110063027
    Abstract: A class-D amplifier for generating from an input signal a digital signal for driving a load, includes an output limit instruction generating section that detects that the digital signal falls outside a limit range and that outputs an output limit instruction signal, an attenuation instruction pulse generating section that includes an integrator for integrating the output limit instruction signal and that outputs a periodical attenuation instruction pulse having pulse width corresponding to an integrated value in the integrator, an attenuating section provided in an input path for the input signal and that attenuates the input signal based on the attenuation instruction pulse, and a mute control section that controls the integrated value in the integrator independently of the output limit instruction signal to control an amount of the attenuation of the attenuating section applied to the input signal.
    Type: Application
    Filed: September 14, 2010
    Publication date: March 17, 2011
    Applicant: Yamaha Corporation
    Inventors: Tatsuya Kishii, Moritaka Iyoda, Hirotoshi Tsuchiya, Toshio Maejima, Masayoshi Nakamura, Masato Miyazaki, Akihisa Himeno
  • Publication number: 20010017756
    Abstract: A hot-line inserting and removing apparatus is capable of inserting and removing a circuit unit while the apparatus is in operation. An overcurrent protection circuit is inserted in a power supply in the hot-line inserting and removing apparatus, and has a switch which changes its resistance to prevent a rush current from flowing into a capacitive component of a connected load for protection against an overcurrent at the time the circuit unit is inserted.
    Type: Application
    Filed: February 26, 2001
    Publication date: August 30, 2001
    Inventor: Moritaka Iyoda
  • Patent number: 5399958
    Abstract: A switching power supply circuit comprising a switching element receiving an electric power from an primary power supply for outputting the received electric power, a smoothing circuit receiving an output of the switching element, a voltage divider receiving a smoothed electric power outputted from the switching element for generating a voltage signal, a comparator having a first input receiving the voltage signal and a second input receiving a reference voltage, for generating a comparison result signal indicating whether or not the voltage signal is larger than the reference voltage, an AND circuit receiving the comparison result signal and a reference oscillation signal, a driver circuit receiving a logical signal from the AND circuit for driving the switching element on the basis of the logical signal, and a feedback circuit receiving the logical signal for feeding back the logical signal to the first input of the comparator.
    Type: Grant
    Filed: May 31, 1994
    Date of Patent: March 21, 1995
    Assignee: NEC Corporation
    Inventor: Moritaka Iyoda