Abstract: A method of manufacturing a trench oxide in a trench for a gate structure in a semiconductor substrate is described. The method includes: generating the trench in the semiconductor substrate; generating an oxide layer over opposing sidewalls of the trench; damaging at least a portion of the oxide layer by ion implantation; coating the oxide layer with an etching mask; generating at least one opening in the etching mask adjacent to one of the opposing sidewalls; and partly removing the oxide layer by etching the oxide layer beneath the etching mask down to an etching depth at the one of the opposing sidewalls by introducing an etching agent into the opening.

Abstract: In an example, a substrate is oriented to a target axis, wherein a residual angular misalignment between the target axis and a preselected crystal channel direction in the substrate is within an angular tolerance interval. Dopant ions are implanted into the substrate using an ion beam that propagates along an ion beam axis. The dopant ions are implanted at implant angles between the ion beam axis and the target axis. The implant angles are within an implant angle range. A channel acceptance width is effective for the preselected crystal channel direction. The implant angle range is greater than 80% of a sum of the channel acceptance width and twofold the angular tolerance interval. The implant angle range is smaller than 500% of the sum of the channel acceptance width and twofold the angular tolerance interval.

Abstract: A method of manufacturing a semiconductor device includes reducing a thickness of a semiconductor substrate and/or forming a doped region in the semiconductor substrate. The method further includes changing an ion acceleration energy of an ion beam while effecting a relative movement between the semiconductor substrate and the ion beam impinging on the semiconductor substrate.

Abstract: A power semiconductor transistor includes a semiconductor body having a front side and a backside with a backside surface. The semiconductor body includes a drift region of a first conductivity type and a field stop region of the first conductivity type. The field stop region is arranged between the drift region and the backside and includes, in a cross-section along a vertical direction from the backside to the front side, a concentration profile of donors of the first conductivity type that has: a first local maximum at a first distance from the backside surface, a front width at half maximum associated with the first local maximum, and a back width at half maximum associated with the first local maximum. The front width at half maximum is smaller than the back width at half maximum and amounts to at least 8% of the first distance.

Abstract: First dopants are implanted through a larger opening of a first process mask into a silicon carbide body, wherein the larger opening exposes a first surface section of the silicon carbide body. A trench is formed in the silicon carbide body in a second surface section exposed by a smaller opening in a second process mask. The second surface section is a sub-section of the first surface section. The larger opening and the smaller opening are formed self-aligned to each other. At least part of the implanted first dopants form at least one compensation layer portion extending parallel to a trench sidewall.

Abstract: A silicon carbide substrate is provided that includes a drift layer of a first conductivity type and a trench extending from a main surface of the silicon carbide substrate into the drift layer. First dopants are implanted through a first trench sidewall of the trench. The first dopants have a second conductivity type and are implanted at a first implant angle into the silicon carbide substrate, wherein at the first implant angle channeling occurs in the silicon carbide substrate. The first dopants form a first compensation layer extending parallel to the first trench sidewall.

Abstract: A method of manufacturing a trench oxide in a trench for a gate structure in a semiconductor substrate is described. The method includes: generating the trench in the semiconductor substrate; generating an oxide layer over opposing sidewalls of the trench; damaging at least a portion of the oxide layer by ion implantation; coating the oxide layer with an etching mask; generating at least one opening in the etching mask adjacent to one of the opposing sidewalls; and partly removing the oxide layer by etching the oxide layer beneath the etching mask down to an etching depth at the one of the opposing sidewalls by introducing an etching agent into the opening.

Abstract: A power semiconductor device includes a semiconductor body having front and back sides. The semiconductor body includes drift, field stop and emitter adjustment regions each of a first conductivity type. The field stop region is arranged between the drift region and the backside and has dopants of the first conductivity type at a higher dopant concentration than the drift region. The emitter adjustment region is arranged between the field stop region and the backside and has dopants of the first conductivity type at a higher dopant concentration than the field stop region. The semiconductor body has a concentration of interstitial oxygen of at least 1E17 cm?3. The field stop region includes a region where the dopant concentration is higher than that in the drift region at least by a factor of three. At least 20% of the dopants of the first conductivity type in the region are oxygen-induced thermal donors.

Abstract: An apparatus and a method for implanting ions are disclosed. In an embodiment, the apparatus includes a receptacle configured to support the wafer, a source of dopants configured to selectively provide dopants to an implantation region of the wafer and a source of radiation configured to selectively irradiate the implantation region.

Abstract: A power semiconductor transistor includes a semiconductor body having a front side and a backside with a backside surface. The semiconductor body includes a drift region of a first conductivity type and a field stop region of the first conductivity type. The field stop region is arranged between the drift region and the backside and includes, in a cross-section along a vertical direction from the backside to the front side, a concentration profile of donors of the first conductivity type that has: a first local maximum at a first distance from the backside surface, a front width at half maximum associated with the first local maximum, and a back width at half maximum associated with the first local maximum. The front width at half maximum is smaller than the back width at half maximum and amounts to at least 8% of the first distance.

Abstract: A semiconductor device includes at least one transistor structure. The at least one transistor structure includes an emitter or source terminal, and a collector or drain terminal. A carbon concentration within a semiconductor substrate region located between the emitter or source terminal and the collector or drain terminal varies between the emitter or source terminal and the collector or drain terminal.

Abstract: A method of manufacturing a semiconductor device includes reducing a thickness of a semiconductor substrate and/or forming a doped region in the semiconductor substrate. The method further includes changing an ion acceleration energy of an ion beam while effecting a relative movement between the semiconductor substrate and the ion beam impinging on the semiconductor substrate.

Abstract: A method of determining the carbon content in a silicon sample may include: generating electrically active polyatomic complexes within the silicon sample. Each polyatomic complex may include at least one carbon atom. The method may further include: determining a quantity indicative of the content of the generated polyatomic complexes in the silicon sample, and determining the carbon content in the silicon sample from the determined quantity.

Abstract: An ion implantation method includes changing an ion acceleration energy and/or an ion beam current density of an ion beam while effecting a relative movement between a semiconductor substrate and the ion beam impinging on a surface of the semiconductor substrate.

Abstract: An implantation apparatus includes a scanning assembly that effects a relative movement between an ion beam and a semiconductor substrate along a first scan direction and along a second scan direction orthogonal to the first scan direction. A tilt assembly changes a tilt angle ? between a beam axis of the ion beam and a normal to a main surface of the semiconductor substrate from a first tilt angle ?1 to a second tilt angle ?2, wherein an angular span ?? between the first tilt angle ?1 and the second tilt angle ?2 is at least 5°. A control unit controls the tilt assembly to continuously change the tilt angle ? during the relative movement between the ion beam and the semiconductor substrate.

Abstract: A method of manufacturing a semiconductor device includes determining information that indicates an extrinsic dopant concentration and an intrinsic oxygen concentration in a semiconductor wafer. On the basis of information about the extrinsic dopant concentration and the intrinsic oxygen concentration as well as information about a generation rate or a dissociation rate of oxygen-related thermal donors in the semiconductor wafer, a process temperature gradient is determined for generating or dissociating oxygen-related thermal donors to compensate for a difference between a target dopant concentration and the extrinsic dopant concentration.

Abstract: Crystal lattice defects are generated in a horizontal surface portion of a semiconductor substrate and hydrogen-related donors are formed in the surface portion. Information is obtained about a cumulative dopant concentration of dopants, including the hydrogen-related donors, in the surface portion. Based on the information about the cumulative dopant concentration and a dissociation rate of the hydrogen-related donors, a main temperature profile is determined for dissociating a defined portion of the hydrogen-related donors. The semiconductor substrate is subjected to a main heat treatment applying the main temperature profile to obtain, in the surface portion, a final total dopant concentration deviating from a target dopant concentration by not more than 15%.

Abstract: A method for forming a semiconductor device includes implanting a predefined dose of protons into a semiconductor substrate. Further, the method comprises controlling a temperature of the semiconductor substrate during the implantation of the predefined dose of protons so that the temperature of the semiconductor substrate is within a target temperature range for more than 70% of an implant process time used for implanting the predefined dose of protons. The target temperature range reaches from a lower target temperature limit to an upper target temperature limit. Further, the lower target temperature limit is equal to a target temperature minus 30° C. and the upper target temperature limit is equal to the target temperature plus 30° C. and the target temperature is higher than 80° C.

Abstract: A method for implanting ions into a semiconductor substrate includes performing a test implantation of ions into a semiconductor substrate. The ions of the test implantation are implanted with a first implantation angle range over the semiconductor substrate. Further, the method includes determining an implantation angle offset based on the semiconductor substrate after the test implantation and adjusting a tilt angle of the semiconductor substrate with respect to an implantation direction based on the determined implantation angle offset. Additionally, the method includes performing at least one target implantation of ions into the semiconductor substrate after the adjustment of the tilt angle. The ions of the at least one target implantation are implanted with a second implantation angle range over the semiconductor substrate. Further, the first implantation angle range is larger than the second implantation angle range.

Abstract: A method for forming a semiconductor device comprises implanting a defined dose of protons into a semiconductor substrate and tempering the semiconductor substrate according to a defined temperature profile. At least one of the defined dose of protons and the defined temperature profile is selected depending on a carbon-related parameter indicating information on a carbon concentration within at least a part of the semiconductor substrate.