Abstract: A high-speed data receiver includes interleaver circuitry configured to divide a received data stream into a plurality of interleaved paths for processing, spectral content detection circuitry configured to derive spectral content information from data on each of the plurality of interleaved paths, sorting circuitry configured to bin the derived spectral content information according to energy levels, stream attribute determination circuitry configured to determine, based on sorted spectral content, one or more of path offsets of the interleaved paths, gain mismatch among interleaved paths, signal bandwidth mismatch and pulse width mismatch, and equalization circuitry configured to correct the one or more of the determined offsets, the determined gain mismatch and the determined signal width mismatch.

Abstract: An integrated circuit transceiver device includes a plurality of functional circuits, and clock circuitry for distributing synchronous, in-phase, phase-locked clock signals to all transceiver circuits. The clock circuitry includes a frequency-controllable distributed oscillator including at least one coupled pair of transmission line oscillators having a respective oscillator core, and at least one respective transmission line segment. At least one impedance element couples the at least one respective transmission line segment of a first transmission line oscillator to the at least one respective transmission line segment of a second transmission line oscillator. Impedance of the impedance element is different from impedance of each respective transmission line segment to cause reflection at the at least one impedance element.

Abstract: A high-speed data receiver includes interleaver circuitry configured to divide a received data stream into a plurality of interleaved paths for processing, spectral content detection circuitry configured to derive spectral content information from data on each of the plurality of interleaved paths, sorting circuitry configured to bin the derived spectral content information according to energy levels, stream attribute determination circuitry configured to determine, based on sorted spectral content, one or more of path offsets of the interleaved paths, gain mismatch among interleaved paths, signal bandwidth mismatch and pulse width mismatch, and equalization circuitry configured to correct the one or more of the determined offsets, the determined gain mismatch and the determined signal width mismatch.

Abstract: An integrated circuit transceiver device includes a plurality of functional circuits, and clock circuitry for distributing synchronous, in-phase, phase-locked clock signals to all transceiver circuits. The clock circuitry includes a frequency-controllable distributed oscillator including at least one coupled pair of transmission line oscillators having a respective oscillator core, and at least one respective transmission line segment. At least one impedance element couples the at least one respective transmission line segment of a first transmission line oscillator to the at least one respective transmission line segment of a second transmission line oscillator. Impedance of the impedance element is different from impedance of each respective transmission line segment to cause reflection at the at least one impedance element.

Abstract: Apparatus and methods for digital-to-analog conversion are disclosed. In one embodiment, an electronic system includes a bias circuit and a digital-to-analog converter (DAC) including an input that receives a digital input signal and an output that drives a transmission line. The digital input signal can be used to control a magnitude and polarity of an output current of the DAC. The DAC further includes one or more p-type metal oxide semiconductor (PMOS) termination transistors that receive a first bias voltage from the bias circuit and one or more n-type metal oxide semiconductor (NMOS) termination transistors that receive a second bias voltage from the bias circuit. The bias circuit controls the voltage levels of the first and second bias voltages to control the termination transistors' small signal resistance to actively terminate the DAC's output.

Abstract: Apparatus and methods for digital-to-analog conversion are disclosed. In one embodiment, an electronic system includes a bias circuit and a digital-to-analog converter (DAC) including an input that receives a digital input signal and an output that drives a transmission line. The digital input signal can be used to control a magnitude and polarity of an output current of the DAC. The DAC further includes one or more p-type metal oxide semiconductor (PMOS) termination transistors that receive a first bias voltage from the bias circuit and one or more n-type metal oxide semiconductor (NMOS) termination transistors that receive a second bias voltage from the bias circuit. The bias circuit controls the voltage levels of the first and second bias voltages to control the termination transistors' small signal resistance to actively terminate the DAC's output.