Patents by Inventor Moshe Agam
Moshe Agam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11289570Abstract: Systems and methods of the disclosed embodiments include a semiconductor device having a semiconductor substrate. The semiconductor substrate has a first major surface, an opposing second major surface, a first doped region of a first conductivity type disposed beneath the first major surface, and a semiconductor region of the first conductivity type disposed between the first doped region and the second major surface. The semiconductor device may also include a trench isolation structure, comprising a conductive trench filling enclosed by an insulating trench liner. The trench isolation structure extends from the first major surface through the first doped region and into the semiconductor region. The semiconductor device may also include a semiconductor device structure disposed with a drain structure, and a connection structure formed between the conductive trench filling of the trench isolation structure and the drain region.Type: GrantFiled: August 24, 2018Date of Patent: March 29, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Johan Camiel Julia Janssens, Jaroslav Pjencak, Moshe Agam
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Patent number: 11251263Abstract: An electronic device can include a substrate defining a trench. In an embodiment, a semiconductor body can be within the trench, wherein the semiconductor body has a resistivity of at least 0.05 ohm-cm and is electrically isolated from the substrate. In an embodiment, an electronic component can be within the semiconductor body. The electronic component can be a resistor or a diode. In a particular embodiment, the semiconductor body has an upper surface, the electronic component is within and along an upper surface and spaced apart from a bottom of the semiconductor body. In a further embodiment, the electronic device can further include a first electronic component within an active region of the substrate, an isolation structure within the trench, and a second electronic component within the isolation structure.Type: GrantFiled: July 18, 2019Date of Patent: February 15, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Moshe Agam, Jaroslav Pjencák, Johan Camiel Julia Janssens
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Publication number: 20210193847Abstract: A semiconductor device may include a Silicon on Insulator (SOI) substrate, and a diode formed on the SOI substrate, the diode including a cathode region and an anode region. The semiconductor device may include at least one breakdown voltage trench disposed at an edge of the cathode region, and between the cathode region and the anode region.Type: ApplicationFiled: March 3, 2021Publication date: June 24, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jaroslav PJENCAK, Moshe AGAM, Johan Camiel Julia JANSSENS
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Publication number: 20210125878Abstract: Manufacturing processes leverage process steps used during CMOS formation to form one or more additional type(s) of devices on the same substrate used for the CMOS formation, and at least partially in parallel with the CMOS formation processes. A first layer of implant wells may be formed at a first depth in a substrate using a first mask, and then a second layer of implant wells may be formed at a second, more shallow depth, using a second mask. CMOS devices that are part of a CMOS platform may be formed using some of the wells, while peripheral devices may be formed using remaining wells.Type: ApplicationFiled: March 27, 2020Publication date: April 29, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Thierry Coffi Herve YAO, Moshe AGAM
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Publication number: 20210125879Abstract: Manufacturing processes leverage process steps used during CMOS formation to form one or more additional type(s) of devices on the same substrate used for the CMOS formation, and at least partially in parallel with the CMOS formation processes. A first layer of implant wells may be formed at a first depth in a substrate using a first mask, and then a second layer of implant wells may be formed at a second, more shallow depth, using a second mask. CMOS devices that are part of a CMOS platform may be formed using some of the wells, while peripheral devices may be formed using remaining wells.Type: ApplicationFiled: March 27, 2020Publication date: April 29, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Moshe AGAM, Thierry Coffi Herve YAO
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Patent number: 10971632Abstract: A semiconductor device may include a Silicon on Insulator (SOI) substrate, and a diode formed on the SOI substrate, the diode including a cathode region and an anode region. The semiconductor device may include at least one breakdown voltage trench disposed at an edge of the cathode region, and between the cathode region and the anode region.Type: GrantFiled: June 24, 2019Date of Patent: April 6, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jaroslav Pjencak, Moshe Agam, Johan Camiel Julia Janssens
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Patent number: 10896954Abstract: An electronic device can include a semiconductor layer having a primary surface, a drift region adjacent to the primary surface, a drain region adjacent to the drift region and extending deeper into the semiconductor layer as compared to the drift region, a resurf region spaced apart from the primary surface, an insulating layer overlying the drain region, and a contact extending through the insulating layer to the drain region. In an embodiment, the drain region can include a sinker region that allows a bulk breakdown to the resurf region to occur during an overvoltage event where the bulk breakdown occurs outside of the drift region, and in a particular embodiment, away from a shallow trench isolation structure or other sensitive structure.Type: GrantFiled: November 5, 2018Date of Patent: January 19, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Moshe Agam, Ladislav {hacek over (S)}eliga, Thierry Coffi Herve Yao, Jaroslav Pjen{hacek over (c)}ák, Gary H. Loechelt
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Publication number: 20200403103Abstract: A semiconductor device may include a Silicon on Insulator (SOI) substrate, and a diode formed on the SOI substrate, the diode including a cathode region and an anode region. The semiconductor device may include at least one breakdown voltage trench disposed at an edge of the cathode region, and between the cathode region and the anode region.Type: ApplicationFiled: June 24, 2019Publication date: December 24, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jaroslav PJENCAK, Moshe AGAM, Johan Camiel Julia JANSSENS
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Patent number: 10818516Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. Trench isolation portions extend from the first major surface and terminate within the semiconductor region to define an active region. An insulated trench structure is laterally disposed between the trench isolation portions, terminates within the floating buried doped region, and defines a first portion and a second portion of the active region. A biasing semiconductor device is within the first portion, and a functional semiconductor device is within the second portion. The biasing semiconductor device is adapted to set a potential of the floating buried doped region and adapted to divert parasitic currents away from the functional semiconductor device.Type: GrantFiled: March 14, 2019Date of Patent: October 27, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Moshe Agam, Johan Camiel Julia Janssens, Bruce Greenwood, Sallie Hose, Agajan Suwhanov
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Publication number: 20200335636Abstract: An electronic device can include a JFET that overlies a substrate and includes a first well region including a drain region or a source region, or both, and a second well region having the opposite the conductivity type. The second well region can be disposed within the first well region and includes a gate electrode of the JFET. Embodiments as described herein can be used to form a JFET integrated with n-channel and p-channel MISFETs without having to add an additional mask or other process operation to an existing process flow.Type: ApplicationFiled: July 1, 2020Publication date: October 22, 2020Applicant: Semiconductor Components Industries, LLCInventor: Moshe Agam
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Publication number: 20200295126Abstract: An electronic device can include a substrate defining a trench. In an embodiment, a semiconductor body can be within the trench, wherein the semiconductor body has a resistivity of at least 0.05 ohm-cm and is electrically isolated from the substrate. In an embodiment, an electronic component can be within the semiconductor body. The electronic component can be a resistor or a diode. In a particular embodiment, the semiconductor body has an upper surface, the electronic component is within and along an upper surface and spaced apart from a bottom of the semiconductor body. In a further embodiment, the electronic device can further include a first electronic component within an active region of the substrate, an isolation structure within the trench, and a second electronic component within the isolation structure.Type: ApplicationFiled: July 18, 2019Publication date: September 17, 2020Applicant: Semiconductor Components Industries, LLCInventors: Moshe Agam, Jaroslav Pjencák, Johan Camiel Julia Janssens
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Publication number: 20200066838Abstract: Systems and methods of the disclosed embodiments include a semiconductor device structure having a semiconductor substrate. The semiconductor substrate has a first major surface, an opposing second major surface, a first doped region of a first conductivity type disposed beneath the first major surface, and a semiconductor region of the first conductivity type disposed between the first doped region and the second major surface. The semiconductor device may also include a trench isolation structure, comprising a conductive trench filling enclosed by an insulating trench liner. The trench isolation structure extends from the first major surface through the first doped region and into the semiconductor region. The semiconductor device may also include a semiconductor device disposed with a drain structure, and a connection structure formed between the conductive trench filling of the trench isolation structure and the drain region.Type: ApplicationFiled: August 24, 2018Publication date: February 27, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Johan Camiel Julia JANSSENS, Jaroslav PJENCAK, Moshe AGAM
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Patent number: 10497780Abstract: In an aspect, a circuit can include a first transistor, wherein an emitter is coupled to an emitter terminal, and a base is coupled to a base terminal; a second transistor, wherein the collector is coupled to a substrate terminal, and a base is coupled to the collector of the first transistor; and a component having a rectifying junction, wherein a first terminal is coupled to the collector of the first transistor, and a second terminal is coupled to the collector terminal of the circuit. In another aspect, an electronic device can include a substrate having a first semiconductor region; a second semiconductor region; and a third semiconductor region; a first trench isolation structure extending from a major surface through the third semiconductor region and terminating within the second semiconductor region; and an emitter region coupled to an emitter terminal of the electronic device.Type: GrantFiled: April 27, 2018Date of Patent: December 3, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Moshe Agam, Agajan Suwhanov, Johan Camiel Julia Janssens
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Patent number: 10490549Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.Type: GrantFiled: January 10, 2019Date of Patent: November 26, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Moshe Agam, Johan Camiel Julia Janssens, Jaroslav Pjencak, Thierry Yao, Mark Griswold, Weize Chen
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Publication number: 20190333992Abstract: In an aspect, a circuit can include a first transistor, wherein an emitter is coupled to an emitter terminal, and a base is coupled to a base terminal; a second transistor, wherein the collector is coupled to a substrate terminal, and a base is coupled to the collector of the first transistor; and a component having a rectifying junction, wherein a first terminal is coupled to the collector of the first transistor, and a second terminal is coupled to the collector terminal of the circuit. In another aspect, an electronic device can include a substrate having a first semiconductor region; a second semiconductor region; and a third semiconductor region; a first trench isolation structure extending from a major surface through the third semiconductor region and terminating within the second semiconductor region; and an emitter region coupled to an emitter terminal of the electronic device.Type: ApplicationFiled: April 27, 2018Publication date: October 31, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Moshe AGAM, Agajan SUWHANOV, Johan Camiel Julia JANSSENS
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Publication number: 20190273169Abstract: An electronic device can include a JFET that overlies a substrate and includes a first well region including a drain region or a source region, or both, and a second well region having the opposite the conductivity type. The second well region can be disposed within the first well region and includes a gate electrode of the JFET. Embodiments as described herein can be used to form a JFET integrated with n-channel and p-channel MISFETs without having to add an additional mask or other process operation to an existing process flow.Type: ApplicationFiled: March 1, 2018Publication date: September 5, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Moshe AGAM
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Publication number: 20190228984Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. Trench isolation portions extend from the first major surface and terminate within the semiconductor region to define an active region. An insulated trench structure is laterally disposed between the trench isolation portions, terminates within the floating buried doped region, and defines a first portion and a second portion of the active region. A biasing semiconductor device is within the first portion, and a functional semiconductor device is within the second portion. The biasing semiconductor device is adapted to set a potential of the floating buried doped region and adapted to divert parasitic currents away from the functional semiconductor device.Type: ApplicationFiled: March 14, 2019Publication date: July 25, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Moshe AGAM, Johan Camiel Julia JANSSENS, Bruce GREENWOOD, Sallie HOSE, Agajan SUWHANOV
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Publication number: 20190148368Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.Type: ApplicationFiled: January 10, 2019Publication date: May 16, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Moshe AGAM, Johan Camiel Julia JANSSENS, Jaroslav PJENCAK, Thierry YAO, Mark GRISWOLD, Weize CHEN
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Patent number: 10276556Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. Trench isolation portions extend from the first major surface and terminate within the semiconductor region to define an active region. An insulated trench structure is laterally disposed between the trench isolation portions, terminates within the floating buried doped region, and defines a first portion and a second portion of the active region. A biasing semiconductor device is within the first portion, and a functional semiconductor device is within the second portion. The biasing semiconductor device is adapted to set a potential of the floating buried doped region and adapted to divert parasitic currents away from the functional semiconductor device.Type: GrantFiled: June 11, 2018Date of Patent: April 30, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Moshe Agam, Johan Camiel Julia Janssens, Bruce Greenwood, Sallie Hose, Agajan Suwhanov
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Publication number: 20190088554Abstract: An electronic device can include a semiconductor layer having a primary surface, a drift region adjacent to the primary surface, a drain region adjacent to the drift region and extending deeper into the semiconductor layer as compared to the drift region, a resurf region spaced apart from the primary surface, an insulating layer overlying the drain region, and a contact extending through the insulating layer to the drain region. In an embodiment, the drain region can include a sinker region that allows a bulk breakdown to the resurf region to occur during an overvoltage event where the bulk breakdown occurs outside of the drift region, and in a particular embodiment, away from a shallow trench isolation structure or other sensitive structure.Type: ApplicationFiled: November 5, 2018Publication date: March 21, 2019Applicant: Semiconductor Components Industries, LLCInventors: Moshe AGAM, Ladislav Seliga, Thierry Coffi Herve Yao, Jaroslav Pjencák, Gary H. Loechelt