Patents by Inventor Moshe Anschel
Moshe Anschel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10193831Abstract: A packet processing system and method for processing data units are provided. A packet processing system includes a processor, first memory having a first latency, and second memory having a second latency that is higher than the first latency. A first portion of a queue for queuing data units utilized by the processor is disposed in the first memory, and a second portion of the queue is disposed in the second memory. A queue manager is configured to push new data units to the second portion of the queue and generate an indication linking a new data unit to an earlier-received data unit in the queue. The queue manager is configured to transfer one or more queued data units from the second portion of the queue to the first portion of the queue prior to popping the queued data unit from the queue, and to update the indication.Type: GrantFiled: January 23, 2015Date of Patent: January 29, 2019Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Itay Peled, Dan Ilan, Michael Weiner, Einat Ophir, Moshe Anschel
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Patent number: 9892083Abstract: Embodiments include a network device comprising: at least one processing core; a packet processing module configured to perform a first set of packet processing operations at a first rate, to partially process data units that are received at the network device, the packet processing module being further configured to transmit ones of the data units to the at least one processing core, the at least one processing core being configured to perform a second set of processing operations at a second rate, wherein the second set of processing operations is different from the first set of processing operations; an interconnecting module configured to interconnect the packet processing module and the at least one processing core; and a rate limiter configured to selectively control a transmission rate at which the data units are transmitted by the packet processing module to the at least one processing core based on the second rate.Type: GrantFiled: March 6, 2015Date of Patent: February 13, 2018Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Itay Peled, Dan Ilan, Moshe Anschel, Michael Weiner, Eitan Joshua
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Circuitry for a computing system, LSU arrangement and memory arrangement as well as computing system
Patent number: 9436624Abstract: A circuitry for a computing system comprising a first load/store unit, LSU, and a second LSU as well as a memory arrangement. The first LSU is connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus. The second LSU is connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus. The computing system is arranged to carry out a multiple load instruction to read data via the first read bus and the second read bus and/or to carry out a multiple store instruction to write data via the first write bus and the second write bus.Type: GrantFiled: July 26, 2013Date of Patent: September 6, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Ziv Zamsky, Moshe Anschel, Itay Keidar, Itay S. Peled, Doron Schupper, Yakov Tokar -
Publication number: 20150215226Abstract: A packet processing system and method for processing data units are provided. A packet processing system includes a processor, first memory having a first latency, and second memory having a second latency that is higher than the first latency. A first portion of a queue for queuing data units utilized by the processor is disposed in the first memory, and a second portion of the queue is disposed in the second memory. A queue manager is configured to push new data units to the second portion of the queue and generate an indication linking a new data unit to an earlier-received data unit in the queue. The queue manager is configured to transfer one or more queued data units from the second portion of the queue to the first portion of the queue prior to popping the queued data unit from the queue, and to update the indication.Type: ApplicationFiled: January 23, 2015Publication date: July 30, 2015Inventors: Itay Peled, Dan Ilan, Michael Weiner, Einat Ophir, Moshe Anschel
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CIRCUITRY FOR A COMPUTING SYSTEM, LSU ARRANGEMENT AND MEMORY ARRANGEMENT AS WELL AS COMPUTING SYSTEM
Publication number: 20150032929Abstract: A circuitry for a computing system comprising a first load/store unit, LSU, and a second LSU as well as a memory arrangement. The first LSU is connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus. The second LSU is connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus. The computing system is arranged to carry out a multiple load instruction to read data via the first read bus and the second read bus and/or to carry out a multiple store instruction to write data via the first write bus and the second write bus.Type: ApplicationFiled: July 26, 2013Publication date: January 29, 2015Inventors: ZIV ZAMSKY, MOSHE ANSCHEL, ITAY KEIDAR, ITAY S. PELED, DORON SCHUPPER, YAKOV TOKAR -
Patent number: 8886895Abstract: A method for fetching information in response to hazard indication information, the method includes: (i) associating hazard indication information to at least one information unit that is being fetched to the cache module; (ii) receiving a request to perform a fetch operation; and (iii) determining whether to fetch at least one information unit to the cache module in response to the hazard indication information and in response to dirty information associated with the at least one information unit.Type: GrantFiled: September 14, 2004Date of Patent: November 11, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Itay Peled, Moshe Anschel, Jacob Efrat, Alon Eldar, Ziv Zamsky
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Patent number: 8832378Abstract: A method for selecting a cache way, the method includes: selecting an initially selected cache way out of multiple cache ways of a cache module for receiving a data unit; the method being characterized by including: searching, if the initially selected cache way is locked, for an unlocked cache way, out of at least one group of cache ways that are located at predefined offsets from the first cache way.Type: GrantFiled: April 11, 2008Date of Patent: September 9, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Rotem Porat, Moshe Anschel, Alon Eldar, Amit Gur, Shai Koren, Itay Peled
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Patent number: 8458407Abstract: A method for generating cache user initiated pre-fetch requests, the method comprises initiating a sequence of user initiated pre-fetch requests; the method being characterized by: determining the timing of user initiated pre-fetch requests of the sequence of user initiated pre-fetch requests in response to: the timing of an occurrence of a last triggering event, a user initiated pre-fetch sequence delay period and a user initiated pre-fetch sequence rate.Type: GrantFiled: March 13, 2007Date of Patent: June 4, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Rotem Porat, Moshe Anschel, Shai Koren, Itay Peled, Erez Steinberg
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Patent number: 8281080Abstract: A system and method for modifying an information unit, the method includes the following stages: (i) receiving, over a first bus, a request to initiate a snooping type atomic operation associated with at least one information unit located at a first address of a memory module; (ii) providing the information unit over the first bus; (iii) attempting to complete the snooping type atomic operation of an updated information unit; and (iv) defining the atomic operation as a failed atomic operation if during at least one stage of receiving, providing and attempting, the first address was locked as a result of a locking type atomic operation.Type: GrantFiled: September 2, 2004Date of Patent: October 2, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Kostantin Godin, Moshe Anschel, Uri Dayan, Dvir Rune R Peleg
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Patent number: 8117400Abstract: A device and a method for fetching an information unit, the method includes: receiving a request to execute a write through cacheable operation of the information unit; emptying a fetch unit from data, wherein the fetch unit is connected to a cache module and to a high level memory unit; determining, when the fetch unit is empty, whether the cache module stores an older version of the information unit; and selectively writing the information unit to the cache module in response to the cache module in response to the determination.Type: GrantFiled: October 20, 2006Date of Patent: February 14, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Ziv Zamsky, Moshe Anschel, Alon Eldar, Dmitry Flat, Kostantin Godin, Itay Peled, Dvir Peleg
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Patent number: 8095769Abstract: A method for address comparison, the method includes: (i) receiving an input address; (ii) determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of each memory segment of the group; (iii) wherein a comparison between the input address and a memory segment boundary comprises: (a) applying a XOR operation on bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary; (b) ignoring bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and (c) comparing, by utilizing a set of full comparators, between bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary; wherein a location of bits that form the intermediate portion of the input address and of the memoType: GrantFiled: August 19, 2008Date of Patent: January 10, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Rotem Porat, Moshe Anschel, Itay Peled, Erez Steinberg, Ziv Zamsky
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Patent number: 8006015Abstract: A device and a method for managing access requests, the method includes: (i) receiving, from a master component coupled to a master bus, multiple access requests to access a slave component over a pipelined slave bus; acknowledging a received access request if: (a) at least an inter-access request delay period lapsed from a last acknowledgement of an access request; (b) an amount of pending acknowledged access requests is below a threshold; wherein the threshold is determined in response to a pipeline depth of the pipelined slave bus; (c) the received access request is valid; wherein a validity of an access request is responsive to a reception of an access request cancellation request; and (ii) providing information from the slave component, in response to at least one acknowledged access request.Type: GrantFiled: November 8, 2006Date of Patent: August 23, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Yaki Devilla, Moshe Anschel, Kostantin Godin, Amit Gur, Itay Peled
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Publication number: 20110040912Abstract: Apparatus and method for bus matching. The method includes: receiving data transfer characteristics at a first endian mode and at a second endian mode; determining a connectivity of multiple devices to an interfacing bus in response to the data transfer characteristics and in response to a relationship between a width of the interfacing bus and a width of each device interface; wherein at least one device interface is connected in parallel to multiple interfacing bus portions; and configuring a control logic such as to provide control signals representative of a transfer of data over the interfacing bus; whereas the control logic is configured in response to the connectivity.Type: ApplicationFiled: September 10, 2004Publication date: February 17, 2011Applicant: Freescale SemiconductorInventors: Kostantin Godin, Moshe Anschel, Jacob Efrat, Itay Peled, Reuven Badash, Asher Bastaker, Dvir Rune Peleg, Ziv Zamsky
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Publication number: 20110022800Abstract: A method for selecting a cache way, the method includes: selecting an initially selected cache way out of multiple cache ways of a cache module for receiving a data unit; the method being characterized by including: searching, if the initially selected cache way is locked, for an unlocked cache way, out of at least one group of cache ways that are located at predefined offsets from the first cache way.Type: ApplicationFiled: April 11, 2008Publication date: January 27, 2011Applicant: Freescale Semiconductor, Inc.Inventors: Rotem Porat, Moshe Anschel, Alon Eldar, Amit Gur, Shai Koren, Itay Peled
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Patent number: 7865691Abstract: A virtual address cache and a method for sharing data. The virtual address cache includes: a memory, adapted to store virtual addresses, task identifiers and data associated with the virtual addresses and the task identifiers; and a comparator, connected to the memory, adapted to determine that data associated with a received virtual address and a received task identifier is stored in the memory if at least a portion of the received virtual address equals at least a corresponding portion of a certain stored virtual address and a stored task identifier associated with the certain stored virtual address indicates that the data is shared between multiple tasks.Type: GrantFiled: August 31, 2004Date of Patent: January 4, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Itay Peled, Moshe Anschel, Moshe Bachar, Jacob Efrat, Alon Eldar, Yakov Tokar
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Publication number: 20100325366Abstract: A device and a method for fetching an information unit, the method includes: receiving a request to execute a write through cacheable operation of the information unit; emptying a fetch unit from data, wherein the fetch unit is connected to a cache module and to a high level memory unit; determining, when the fetch unit is empty, whether the cache module stores an older version of the information unit; and selectively writing the information unit to the cache module in response to the cache module in response to the determination.Type: ApplicationFiled: October 20, 2006Publication date: December 23, 2010Inventors: Ziv Zamsky, Moshe Anschel, Alon Eldar, Dmitry Flat, Kostantin Godin, Itay Peled, Dvir Peleg
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Publication number: 20100250806Abstract: A device and a method for managing access requests, the method includes: (i) receiving, from a master component coupled to a master bus, multiple access requests to access a slave component over a pipelined slave bus; acknowledging a received access request if: (a) at least an inter-access request delay period lapsed from a last acknowledgement of an access request; (b) an amount of pending acknowledged access requests is below a threshold; wherein the threshold is determined in response to a pipeline depth of the pipelined slave bus; (c) the received access request is valid; wherein a validity of an access request is responsive to a reception of an access request cancellation request; and (ii) providing information from the slave component, in response to at least one acknowledged access request.Type: ApplicationFiled: November 8, 2006Publication date: September 30, 2010Applicant: Freescale Semiconductor, Inc.Inventors: Yaki Devilla, Moshe Anschel, Kostantin Godin, Amit Gur, Italy Peled
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Publication number: 20100122037Abstract: A method for generating cache user initiated pre-fetch requests, the method comprises initiating a sequence of user initiated pre-fetch requests; the method being characterized by: determining the timing of user initiated pre-fetch requests of the sequence of user initiated pre-fetch requests in response to: the timing of an occurrence of a last triggering event, a user initiated pre-fetch sequence delay period and a user initiated pre-fetch sequence rate.Type: ApplicationFiled: March 13, 2007Publication date: May 13, 2010Applicant: Freescale Semiconductor, Inc.Inventors: Rotem Porat, Moshe Anschel, Shai Koren, Itay Peled, Erez Steinberg
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Patent number: 7716453Abstract: A memory management unit that includes: (i) multiple data segment descriptors, each data segment descriptor associated with a data memory segment; (ii) multiple program segment descriptors, each program segment descriptor associated with a program memory segment; and (iii) a controller, adapted to replace the content of the multiple data segment descriptors and the multiple program segment descriptors in response to a task switch.Type: GrantFiled: September 10, 2004Date of Patent: May 11, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Moshe Anschel, Moshe Bachar, Uri Dayan, Jacob Efrat, Itay Peled, Zvika Rozenshein
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Publication number: 20100049939Abstract: A method for address comparison, the method includes: (i) receiving an input address; (ii) determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of each memory segment of the group; (iii) wherein a comparison between the input address and a memory segment boundary comprises: (a) applying a XOR operation on bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary; (b) ignoring bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and (c) comparing, by utilizing a set of full comparators, between bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary; wherein a location of bits that form the intermediate portion of the input address and of the memoType: ApplicationFiled: August 19, 2008Publication date: February 25, 2010Inventors: Rotem Porat, Moshe Anschel, Itay Peled, Erez Steinberg, Ziv Zamsky