Patents by Inventor Moto Yabuki

Moto Yabuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7960779
    Abstract: A nonvolatile semiconductor memory of an aspect of the invention includes memory cells in the memory cell forming area, and select gate transistors in the select gate forming area. Each memory cell has two first diffusion layers formed in a semiconductor substrate, a first gate insulating film formed on the semiconductor substrate, a charge storage layer formed on the first gate insulating film, a first intermediate insulating film formed on the charge storage layer and a first gate electrode formed on the first intermediate insulating film. Each select gate transistor has two second diffusion layers formed in the semiconductor substrate, a second gate insulating film formed on the semiconductor substrate, a second intermediate insulating film formed in direct contact with the second gate insulating film and having the same structure as the first intermediate insulating film, and a second gate electrode formed on the second intermediate insulating film.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: June 14, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Toba, Takayuki Okamura, Moto Yabuki
  • Patent number: 7915156
    Abstract: A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: March 29, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Aoyama, Eiji Ito, Masahiro Kiyotoshi, Tadashi Iguchi, Moto Yabuki
  • Publication number: 20090218607
    Abstract: A nonvolatile semiconductor memory of an aspect of the invention includes memory cells in the memory cell forming area, and select gate transistors in the select gate forming area. Each memory cell has two first diffusion layers formed in a semiconductor substrate, a first gate insulating film formed on the semiconductor substrate, a charge storage layer formed on the first gate insulating film, a first intermediate insulating film formed on the charge storage layer and a first gate electrode formed on the first intermediate insulating film. Each select gate transistor has two second diffusion layers formed in the semiconductor substrate, a second gate insulating film formed on the semiconductor substrate, a second intermediate insulating film formed in direct contact with the second gate insulating film and having the same structure as the first intermediate insulating film, and a second gate electrode formed on the second intermediate insulating film.
    Type: Application
    Filed: February 26, 2009
    Publication date: September 3, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Toba, Takayuki Okamura, Moto Yabuki
  • Publication number: 20090212352
    Abstract: A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.
    Type: Application
    Filed: February 24, 2009
    Publication date: August 27, 2009
    Inventors: Kenji AOYAMA, Eiji Ito, Masahiro Kiyotoshi, Tadashi Iguchi, Moto Yabuki
  • Publication number: 20060065980
    Abstract: Disclosed is a semiconductor device comprising an underlying film, a first electrode formed on the underlying film, a first dielectric film formed on the first electrode, a second electrode formed on the first dielectric film, and a first interconnect including a first conductive portion extending in a stack direction of the first electrode, the first dielectric film and the second electrode, a side surface of the first conductive portion being in contact with one of the first electrode and the second electrode.
    Type: Application
    Filed: November 14, 2005
    Publication date: March 30, 2006
    Inventor: Moto Yabuki
  • Publication number: 20050127513
    Abstract: Disclosed is a semiconductor device comprising an underlying film, a first electrode formed on the underlying film, a first dielectric film formed on the first electrode, a second electrode formed on the first dielectric film, and a first interconnect including a first conductive portion extending in a stack direction of the first electrode, the first dielectric film and the second electrode, a side surface of the first conductive portion being in contact with one of the first electrode and the second electrode.
    Type: Application
    Filed: January 26, 2005
    Publication date: June 16, 2005
    Inventor: Moto Yabuki
  • Patent number: 6906908
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate, an insulation region which covers the capacitor and has a first hole and a second hole, the first hole being provided apart from the capacitor and extending in a vertical direction with respect to a main surface of the semiconductor substrate, the second hole reaching an electrode of the capacitor, extending in the vertical direction with respect to the main surface of the semiconductor substrate and being shallower than the first hole, a tungsten plug provided in the first hole, a first oxygen barrier film provided between the tungsten plug and a side wall of the first hole, and a conductive plug provided in the second hole and connected to the electrode of the capacitor.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: June 14, 2005
    Assignees: Kabushiki Kaisha Toshiba, Infineon Technologies, AG
    Inventors: Moto Yabuki, Andreas Hilliger
  • Publication number: 20040171252
    Abstract: An improved method of reducing contamination in processing of ICs is disclosed. The method includes forming a contamination protection layer on at least the back surface of the substrate. The contamination protection layer comprises a low diffusion factor and can be cleaned efficiently. In one embodiment, the contamination protection layer comprises HCD silicon nitride.
    Type: Application
    Filed: February 28, 2003
    Publication date: September 2, 2004
    Inventors: Haoren Zhuang, Katsuaki Natori, Gerhard Beitel, Bum-ki Moon, Moto Yabuki, Yoshitaka Tsunashima, Karl Hornik
  • Publication number: 20040159874
    Abstract: Disclosed is a semiconductor device comprising an insulating film, a capacitor formed on the insulating film and comprising a bottom electrode, a top electrode, and a dielectric film between the top electrode and the bottom electrode, a plug passing through the insulating film and connected to the bottom electrode, and an oxygen barrier film covering the capacitor and the insulating film, and having lower oxygen permeability than the insulating film.
    Type: Application
    Filed: August 7, 2003
    Publication date: August 19, 2004
    Inventors: Takamichi Tsuchiya, Moto Yabuki
  • Publication number: 20040135185
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the top electrode and the bottom electrode, an insulating region surrounding the capacitor and having a first hole which extends in a vertical direction and reaches the top electrode and a second hole which extends in the vertical direction and is spaced away from the capacitor, and a first wiring connected to the top electrode and including a first conductive portion formed in the first hole and a second conductive portion formed in the second hole, the first wiring having a barrier metal film between the insulating region and the first conductive portion and having no barrier metal film between the insulating region and the second conductive portion.
    Type: Application
    Filed: October 10, 2003
    Publication date: July 15, 2004
    Inventor: Moto Yabuki
  • Publication number: 20040124536
    Abstract: Disclosed is a semiconductor device comprising an underlying film, a first electrode formed on the underlying film, a first dielectric film formed on the first electrode, a second electrode formed on the first dielectric film, and a first interconnect including a first conductive portion extending in a stack direction of the first electrode, the first dielectric film and the second electrode, a side surface of the first conductive portion being in contact with one of the first electrode and the second electrode.
    Type: Application
    Filed: October 10, 2003
    Publication date: July 1, 2004
    Inventor: Moto Yabuki
  • Patent number: 6614642
    Abstract: A capacitor over plug (COP) structure is disclosed. The COP avoids the step which is created in conventional COP structures, which adversely impacts the properties of the capacitor. In one embodiment, the step is avoided by providing a plug having upper and lower portions. The upper portion, which is coupled to the bottom electrode of the capacitor, has substantially the same surface area as the bottom electrode. A barrier layer can be provided between the plug and bottom electrode to avoid oxidation of the plug material.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: September 2, 2003
    Assignees: Infineon Technologies Aktiengesellschaft, Kabushiki Kaisha Toshiba
    Inventors: Bum-ki Moon, Moto Yabuki, Gerhard Beitel, Nicolas Nagel, Andreas Hilliger, Takamichi Tsuchiya
  • Patent number: 6093243
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: July 25, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 6066872
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: May 23, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 5879447
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 9, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 5854133
    Abstract: According to the present invention, to flatten the surface of a silicon substrate by polishing an element isolating buried insulation film by chemical mechanical polishing, a polysilicon film is formed on the top surface of a projection of a silicon substrate. After that, a buried insulation film is formed all over the silicon substrate along the irregularities thereof. A carbon film is formed on the surface of a recess of the buried insulation film. Using the carbon film as a stopper, the buried insulation film is polished by the chemical mechanical polishing to ease the irregularities of the surface of the polished insulation film. Then the carbon film is removed and, using the polysilicon film as a stopper, the buried insulation film is polished by the chemical mechanical polishing to flatten the surface of the polished insulation film. Thus, the flatness of the buried insulation film can easily be controlled, and the surface of the silicon substrate can always be flattened satisfactorily.
    Type: Grant
    Filed: August 15, 1996
    Date of Patent: December 29, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayo Hachiya, Moto Yabuki, Hiroyuki Kamijou
  • Patent number: 5582640
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: December 10, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano