Abstract: In a computer system of the present invention, CPUs of a single or a plurality of host computers access the shared IO devices connected to a shared IO bus of each shared IO device in the same manner as the host IO device in each host computer connected to the host IO bus. Each of the CPUs selects one of the host IO devices and shared IO devices by IO addressing to issue a transaction; each of the IO host adaptors gives the transaction a host number when the transaction is issued to each of the shared IO devices; and an IO port adaptor analyzes the host number of the transaction issued for each of the IO devices to decide to return said transaction to which of the plurality of host computers.

Abstract: A multi-memory apparatus, configured only with identical memory units with access to the common system bus, provides secure data identity in the event of various errors by using synchronous as well as parallel operation. A memory unit in a multi-memory apparatus includes a refresh request circuit, a bus control circuit, a bus-response circuit as well as a control circuit. A master refresh request circuit issues a memory-refresh request by using the bus clock and a backup refresh request circuit issues a memory-refresh request by a trigger from the master memory. A master bus control circuit responds to the system bus and a backup bus control circuit prohibits the unit from responding. A master bus-response control circuit allows the bus control circuit to respond to the system bus and changes mode between memory units from master/backup to backup/master in the event of an error detected in the master memory unit.