Abstract: To improve the convenience of using a memory module, there are provided indicator elements corresponding to types of access to semiconductor memory. The indicator elements are configured to correspond to the access type and indicate the frequency of this type of access to the semiconductor memory. The indicator elements are also configured to indicate the frequency of access to the semiconductor memory and hold an indication corresponding to the maximum frequency of the access. Furthermore, the indicator elements are configured to indicate the frequency of access to the semiconductor memory when a connection terminal 22 is connected to a motherboard connector 91 and a memory module connection terminal 82 is connected to a connector 23.

Abstract: A computer body outputting a predetermined number of address signals A0 to A11 and a plurality of select signals CSO and CSI, generates a memory select signal CS and an additional address signal A12 added to the signals A0 to A11 according to the inputted signals CSO and CSI, and provides the signal CS, signal A12, and signals A0 to AI1 to a 256-megabit SDRAM (memory), so that the computer body can access the corresponding data. The computer body can access the data corresponding to the generated additional address signal A12 and predetermined number of the address signals A0 to A11.

Abstract: To improve the convenience of using a memory module, there are provided indicator elements corresponding to types of access to semiconductor memory. The indicator elements are configured to correspond to the access type and indicate the frequency of this type of access to the semiconductor memory. The indicator elements are also configured to indicate the frequency of access to the semiconductor memory and hold an indication corresponding to the maximum frequency of the access. Furthermore, the indicator elements are configured to indicate the frequency of access to the semiconductor memory when a connection terminal 22 is connected to a motherboard connector 91 and a memory module connection terminal 82 is connected to a connector 23.

Abstract: To improve the convenience of using a memory module, there are provided indicator elements corresponding to types of access to semiconductor memory. The indicator elements are configured to correspond to the access type and indicate the frequency of this type of access to the semiconductor memory. The indicator elements are also configured to indicate the frequency of access to the semiconductor memory and hold an indication corresponding to the maximum frequency of the access. Furthermore, the indicator elements are configured to indicate the frequency of access to the semiconductor memory when a connection terminal 22 is connected to a motherboard connector 91 and a memory module connection terminal 82 is connected to a connector 23.

Abstract: A computer body outputting only address signals A0 to A11 could use only a half area of a 256-megabit SDRAM. The memory circuit 30 receives a predetermined number of address signals A0 to A11 and a plurality of select signals CS0 and CS1, generates a memory select signal CS and an additional address signal A12 added to the signals A0 to A11 according to the inputted signals CS0 and CS1, and provides the signal CS, signal A12, and signals A0 to A11 to a 256-megabit SDRAM (memory), so that the computer body can access the corresponding data. The computer body can access the data corresponding to the generated additional address signal A12 and predetermined number of the address signals A0 to A11.

Abstract: To improve the convenience of using a memory module, there are provided indicator elements corresponding to types of access to semiconductor memory. The indicator elements are configured to correspond to the access type and indicate the frequency of this type of access to the semiconductor memory. The indicator elements are also configured to indicate the frequency of access to the semiconductor memory and hold an indication corresponding to the maximum frequency of the access. Furthermore, the indicator elements are configured to indicate the frequency of access to the semiconductor memory when a connection terminal 22 is connected to a motherboard connector 91 and a memory module connection terminal 82 is connected to a connector 23.

Abstract: It is aimed at not only enabling access to an inaccessible SDRAM area from a PC which only outputs A0 through A11 signals, but also making a common memory module connectable to earlier or latest PCs independently of their models. According to the construction, a connected PC (computer) inputs a high-order address signal A12. It is determined whether or not the input A12 signal is set to a state different from an unused state. A determination signal is generated so as to indicate a state corresponding to a determination result. When the determination signal indicates a changed state, the PC inputs A0 through A12 signals and supplies them to a memory chip 20. When the determination signal indicates an unchanged state, the PC inputs A0 through A11 signals and a select signal. The A12 signal is generated based on the input select signal. The memory chip 20 is supplied with the A12 signal and the input A0 through A11 signals.