Patents by Inventor Motoi Kudoh
Motoi Kudoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6528826Abstract: A depletion type MOS semiconductor device is provided which includes a p− well region formed in a surface layer of an n− drift layer, an n+ emitter region formed in a surface layer of the p31 well region, an n− depletion region formed in the surface layer of the p− well region, to extend from the n+ emitter region to a surface layer of the n− drift layer, a gate electrode layer formed on a gate insulating film, over the n− depletion region, an emitter electrode formed in contact with surfaces of both of the n+ emitter region and the p− well region, and a collector electrode formed on a rear surface of the n− drift layer. Also provided is a MOS power IC in which the depletion type MOS semiconductor device is integrated with a vertical MOSFET or IGBT. The MOS power IC has a high breakdown voltage, and includes a circuit for feeding back an increase in the potential of the C terminal to the gate (gm) of the MOSFET or IGBT.Type: GrantFiled: March 6, 2001Date of Patent: March 4, 2003Assignee: Fuji Electric Co., Ltd.Inventors: Kazuhiko Yoshida, Motoi Kudoh, Tatsuhiko Fijihira
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Patent number: 6462382Abstract: A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.Type: GrantFiled: March 19, 2001Date of Patent: October 8, 2002Assignee: Fuji Electric Co., Ltd.Inventors: Kazuhiko Yoshida, Tatsuhiko Fujihira, Motoi Kudoh, Shoichi Furuhata, Shigeyuki Takeuchi
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Publication number: 20010042886Abstract: A depletion type MOS semiconductor device is provided which includes a p− well region formed in a surface layer of an n− drift layer, an n+ emitter region formed in a surface layer of the p− well region, an n− depletion region formed in the surface layer of the p− well region, to extend from the n+ emitter region to a surface layer of the n− drift layer, a gate electrode layer formed on a gate insulating film, over the n− depletion region, an emitter electrode formed in contact with surfaces of both of the n+ emitter region and the p− well region, and a collector electrode formed on a rear surface of the n− drift layer. Also provided is a MOS power IC in which the depletion type MOS semiconductor device is integrated with a vertical MOSFET or IGBT. The MOS power IC has a high breakdown voltage, and includes a circuit for feeding back an increase in the potential of the C terminal to the gate (gm) of the MOSFET or IGBT.Type: ApplicationFiled: March 6, 2001Publication date: November 22, 2001Applicant: Fuji Electric, Co., Ltd.Inventors: Kazuhiko Yoshida, Motoi Kudoh, Tatsuhiko Fujihira
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Publication number: 20010010379Abstract: A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.Type: ApplicationFiled: March 19, 2001Publication date: August 2, 2001Applicant: Fuji Electric, Co., Ltd.Inventors: Kazuhiko Yoshida, Tatsuhiko Fujihira, Motoi Kudoh, Shoichi Furuhata, Shigeyuki Takeuchi
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Patent number: 6268628Abstract: A depletion type MOS semiconductor device is provided which includes a p− well region formed in a surface layer of an n− drift layer, an n+ emitter region formed in a surface layer of the p− well region, an n− depletion region formed in the surface layer of the p well region, to extend from the n+ emitter region to a surface layer of the n drift layer, a gate electrode layer formed on a gate insulating film, over the n− depletion region, an emitter electrode formed in contact with surfaces of both of the n+ emitter region and the p− well region, and a collector electrode formed on a rear surface of the n− drift layer. Also provided is a MOS power IC in which the depletion type MOS semiconductor device is integrated with a vertical MOSFET or IGBT. The MOS power IC has a high breakdown voltage, and includes a circuit for feeding back an increase in the potential of the C terminal to the gate (gm) of the MOSFET or IGBT.Type: GrantFiled: April 5, 1999Date of Patent: July 31, 2001Assignee: Fuji Electric Co., Ltd.Inventors: Kazuhiko Yoshida, Motoi Kudoh, Tatsuhiko Fijihira
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Patent number: 6229180Abstract: A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.Type: GrantFiled: January 27, 1999Date of Patent: May 8, 2001Assignee: Fuji Electric Co., Ltd.Inventors: Kazuhiko Yoshida, Tatsuhiko Fujihira, Motoi Kudoh, Shoichi Furuhata, Shigeyuki Takeuchi