Patents by Inventor Motoki Fujii

Motoki Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230276627
    Abstract: A semiconductor device according to the present embodiment comprises a stack including a plurality of electrode films stacked in a first direction to be separated from each other. A column portion extends in the stack in the first direction and includes a semiconductor layer, and has memory cells at respective intersections of the semiconductor layer and the electrode films. A dividing portion extends in the stack in the first direction and a second direction crossing the first direction, divides the electrode films in a third direction crossing the first direction and the second direction, and includes an insulator. A first film is provided between the insulator and an end surface in the third direction of each of the electrode films and contains a first metal and silicon.
    Type: Application
    Filed: September 1, 2022
    Publication date: August 31, 2023
    Applicant: Kioxia Corporation
    Inventors: Takashi FUKUSHIMA, Kaihei KATOU, Kenichiro TORATANI, Ryota FUJITSUKA, Junya FUJITA, Atsushi FUKUMOTO, Motoki FUJII, Yuki WAKISAKA, Kazuya HATANO
  • Publication number: 20220270885
    Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a substrate processor configured to process a substrate with a gas of a first substance and a gas of a second substance, and discharge a first gas including the first substance and/or the second substance. The apparatus further includes a disposer configured to discard the first gas discharged from the substrate processor. The apparatus further includes a recoverer configured to generate a second gas including the second substance by using the first substance in the first gas discharged from the substrate processor, and supply the second gas to the substrate processor.
    Type: Application
    Filed: September 14, 2021
    Publication date: August 25, 2022
    Applicant: Kioxia Corporation
    Inventors: Motoki FUJII, Hiroshi KUBOTA, Fumiki AISO
  • Publication number: 20220084799
    Abstract: A semiconductor manufacturing apparatus according to an embodiment includes: a chamber that houses a semiconductor substrate; and a plurality of coils provided on a lateral surface of the chamber. The chamber has a first spatial region enclosed above the semiconductor substrate by a first coil that is one of the plurality of coils, a first gas introduction port communicating with the first spatial region, a second spatial region enclosed by a second coil that is different from the first coil among the plurality of coils, and a second gas introduction port communicating with the second spatial region.
    Type: Application
    Filed: September 3, 2021
    Publication date: March 17, 2022
    Applicant: Kioxia Corporation
    Inventors: Motoki FUJII, Daisuke NISHIDA
  • Patent number: 11195744
    Abstract: A substrate treatment apparatus according to an embodiment of the present invention includes a chamber, a stage, a gas discharger, a plasma generator, and a rotation mechanism. The stage supports a semiconductor substrate in the chamber. The gas discharger discharges a film formation gas toward the semiconductor substrate from a position opposing the stage. The plasma generator is provided on the gas discharger and generates plasma in the chamber during discharge of the film formation gas. The rotation mechanism rotates the stage during generation of the plasma.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: December 7, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Motoki Fujii, Takuo Ohashi, Daisuke Nishida
  • Publication number: 20200075391
    Abstract: A substrate treatment apparatus according to an embodiment of the present invention includes a chamber, a stage, a gas discharger, a plasma generator, and a rotation mechanism. The stage supports a semiconductor substrate in the chamber. The gas discharger discharges a film formation gas toward the semiconductor substrate from a position opposing the stage. The plasma generator is provided on the gas discharger and generates plasma in the chamber during discharge of the film formation gas. The rotation mechanism rotates the stage during generation of the plasma.
    Type: Application
    Filed: February 22, 2019
    Publication date: March 5, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Motoki FUJII, Takuo OHASHI, Daisuke NISHIDA
  • Patent number: 9920427
    Abstract: A semiconductor manufacturing apparatus according to an embodiment comprises a reaction chamber in which a semiconductor substrate is capable of being accommodated when a deposited film is to be formed on a surface of the semiconductor substrate. A first supplier supplies a source gas to a first area in the reaction chamber. A second supplier supplies an oxidation gas to a second area in the reaction chamber. A third supplier supplies a hydrogen gas to a third area between the first area and the second area in the reaction chamber. A stage moves the semiconductor substrate to any one of the first to third areas.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 20, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Motoki Fujii, Fumiki Aiso, Hajime Nagano, Ryota Fujitsuka
  • Publication number: 20160222514
    Abstract: A semiconductor manufacturing apparatus according to an embodiment comprises a reaction chamber in which a semiconductor substrate is capable of being accommodated when a deposited film is to be formed on a surface of the semiconductor substrate. A first supplier supplies a source gas to a first area in the reaction chamber. A second supplier supplies an oxidation gas to a second area in the reaction chamber. A third supplier supplies a hydrogen gas to a third area between the first area and the second area in the reaction chamber. A stage moves the semiconductor substrate to any one of the first to third areas.
    Type: Application
    Filed: June 26, 2015
    Publication date: August 4, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Motoki FUJII, Fumiki AISO, Hajime NAGANO, Ryota FUJITSUKA
  • Patent number: 9263319
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of stacked bodies and a spacer film provided on a side surface of the stacked bodies. Each of the plurality of stacked bodies includes a silicon electrode and a metal electrode stacked on the metal electrode. The plurality of stacked bodies are separated from each other by an air gap. The spacer film includes silicon oxide. A portion of the spacer film disposed on a side surface of the metal electrode is thicker than a portion of the spacer film disposed on a side surface of the silicon electrode.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: February 16, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Fujitsuka, Fumiki Aiso, Motoki Fujii, Hiroshi Itokawa
  • Publication number: 20150060986
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of stacked bodies and a spacer film provided on a side surface of the stacked bodies. Each of the plurality of stacked bodies includes a silicon electrode and a metal electrode stacked on the metal electrode. The plurality of stacked bodies are separated from each other by an air gap. The spacer film includes silicon oxide. A portion of the spacer film disposed on a side surface of the metal electrode is thicker than a portion of the spacer film disposed on a side surface of the silicon electrode.
    Type: Application
    Filed: June 9, 2014
    Publication date: March 5, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryota FUJITSUKA, Fumiki AISO, Motoki FUJII, Hiroshi ITOKAWA
  • Publication number: 20130092999
    Abstract: A nonvolatile storage device includes a tunnel insulating film disposed on a surface of a semiconductor substrate and a charge trap layer disposed in contact with an upper surface of the tunnel insulating film. The charge trap layer includes a second charge trap film disposed in contact with the upper surface of the tunnel insulating film and a first charge trap film disposed in contact with an upper surface of the second charge trap film.
    Type: Application
    Filed: September 12, 2012
    Publication date: April 18, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Motoki FUJII
  • Publication number: 20120164848
    Abstract: A plasma-assisted ALD method using a vertical furnace and being performed by repeating a cycle until a desired film thickness is obtained is disclosed. The cycle comprises introducing a source gas containing a source to be nitrided, adsorbing, purging, introducing a nitriding gas and nitriding the source, and then, purging. A flow rate of a second carrier gas during introduction of the nitriding gas is reduced relative to that of a first carrier gas during introduction of the source gas. Particularly, a flow ratio of NH3 gas as the nitriding gas to N2 gas as the second carrier gas is 50:3 or less.
    Type: Application
    Filed: December 28, 2011
    Publication date: June 28, 2012
    Applicants: Tokyo Electron Limited, Elpida Memory, Inc.
    Inventors: Motoki FUJII, Masanobu MATSUNAGA, Kazuya YAMAMOTO, Kota UMEZAWA
  • Patent number: 6809160
    Abstract: A resin composition comprises a resin (A) and a resin (B) as constituents, said resin (A) having a number average molecular weight of 1,000 to 35,000 and being at least one member selected from the group consisting of following (A1) and (A2): (A1) a polyester polyol, a polyether polyol, a polycarbonate polyol, a polyurethane polyol, a polyolefin polyol and an acrylic polyol, (A2) a polymer obtained by reacting said (A1) with a compound having at least one functional group selected from the group consisting of isocyanato, carboxyl and epoxy groups within a molecule thereof, a dialkyl carbonate, a cyclic carbonate, an alcohol, or a mixture of these, and said resin (B) having a sulfonium group and a propargyl group within the molecule thereof.
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: October 26, 2004
    Assignee: Nippon Paint Co., Ltd.
    Inventors: Noriyuki Tsuboniwa, Motoki Fujii, Ichiro Kawakami, Takayuki Kokubun, Hiroyuki Sakamoto
  • Patent number: 6790329
    Abstract: It is an object of the present invention to provide a method of forming a coating film by which a coating film excellent in weathering resistance, light degradation resistance, smoothness and the like can be formed on the outer panel portion of an article to be coated such as a car, and a coating film excellent in rust prevention can be formed on the inner panel portion (bag-structured portion) of the article to be coated, with the interface between the outer and inner panel portions of the article being excellent in rust prevention and finish as well, and by which resources saving and coating cost reduction can be expected.
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: September 14, 2004
    Assignee: Nippon Paint Co., Ltd.
    Inventors: Hiroyuki Sakamoto, Noriyuki Tsuboniwa, Motoki Fujii, Kazuo Morichika, Ichiro Kawakami
  • Publication number: 20020188070
    Abstract: It is an object of the present invention to provide a resin composition excellent in throwing power as well as corrosion prevention and capable of providing coating films excellent in impact resistance, and a cationic electrodeposition coating composition containing the resin composition.
    Type: Application
    Filed: November 26, 2001
    Publication date: December 12, 2002
    Applicant: NIPPON PAINT CO., LTD.
    Inventors: Noriyuki Tsuboniwa, Motoki Fujii, Ichiro Kawakami, Takayuki Kokubun, Hiroyuki Sakamoto
  • Publication number: 20020098363
    Abstract: It is an object of the present invention to provide a method of forming a coating film by which a coating film excellent in weathering resistance, light degradation resistance, smoothness and the like can be formed on the outer panel portion of an article to be coated such as a car, and a coating film excellent in rust prevention can be formed on the inner panel portion (bag-structured portion) of the article to be coated, with the interface between the outer and inner panel portions of the article being excellent in rust prevention and finish as well, and by which resources saving and coating cost reduction can be expected.
    Type: Application
    Filed: November 26, 2001
    Publication date: July 25, 2002
    Applicant: NIPPON PAINT CO., LTD.
    Inventors: Hiroyuki Sakamoto, Noriyuki Tsuboniwa, Motoki Fujii, Kazuo Morichika, Ichiro Kawakami