Abstract: A plasma processing apparatus comprises a base including an electrode body having a seat surface for setting a substrate held on a conveying carrier, and a platform for supporting the electrode body, and a lid configured to be moved up and down relative to the base, wherein the lid is moved down and appressed on the platform to define a closed space and a plasma is generated within the closed space to implement a plasma processing for the substrate set on the seat surface. The substrate is held on the holding sheet and set on the seat surface with the holding sheet therebetween. The plasma processing apparatus further comprises a guide being provided along a circumference of the electrode body for alignment of the frame, and a cover provided with the lid for covering at least the frame of the conveying carrier when the closed space is defined.

Abstract: A plasma processing apparatus includes: a base that has an electrode body provided with a placing surface on which a substrate is placed and a pedestal which supports the electrode body; a lid that is liftable and lowerable with respect to the base and forms a sealed space for performing plasma processing on the substrate placed on the placing surface by being lowered to come into close contact with the pedestal; a cover that is provided integrally with the lid and covers at least a part of an outer edge of the substrate placed on the placing surface when the sealed space is formed; and a guide that is disposed around the electrode body.

Abstract: A branching structure for connecting a branch harness to a main line harness, includes connection terminals configured to electrically connect branch lines of the branch harness to main lines of the main line harness respectively, a terminal block on which the connection terminals are supported, and fasteners that respectively fasten the connection terminals onto the terminal block. Each of the connection terminals has a belt-shaped wound portion to be wound around a corresponding one of the main lines. The wound portion is fastened by a corresponding one of the fasteners so that both ends of the wound portion come closer to each other and a center portion of the wound portion tightens around the main line so as to be brought into surface contact with a bar conductor of the main line.

Abstract: A plasma processing apparatus includes: a base that has an electrode body provided with a placing surface on which a substrate is placed and a pedestal which supports the electrode body; a lid that is liftable and lowerable with respect to the base and forms a sealed space for performing plasma processing on the substrate placed on the placing surface by being lowered to come into close contact with the pedestal; a cover that is provided integrally with the lid and covers at least a part of an outer edge of the substrate placed on the placing surface when the sealed space is formed; and a guide that is disposed around the electrode body.

Abstract: A branching structure for connecting a branch harness to a main line harness, includes connection terminals configured to electrically connect branch lines of the branch harness to main lines of the main line harness respectively, a terminal block on which the connection terminals are supported, and fasteners that respectively fasten the connection terminals onto the terminal block. Each of the connection terminals has a belt-shaped wound portion to be wound around a corresponding one of the main lines. The wound portion is fastened by a corresponding one of the fasteners so that both ends of the wound portion come closer to each other and a center portion of the wound portion tightens around the main line so as to be brought into surface contact with a bar conductor of the main line.

Abstract: A plasma processing apparatus comprises a base including an electrode body having a seat surface for setting a substrate held on a conveying carrier, and a platform for supporting the electrode body, and a lid configured to be moved up and down relative to the base, wherein the lid is moved down and appressed on the platform to define a closed space and a plasma is generated within the closed space to implement a plasma processing for the substrate set on the seat surface. The substrate is held on the holding sheet and set on the seat surface with the holding sheet therebetween. The plasma processing apparatus further comprises a guide being provided along a circumference of the electrode body for alignment of the frame, and a cover provided with the lid for covering at least the frame of the conveying carrier when the closed space is defined.

Abstract: A command decoder receives an externally supplied command independently of an internal clock signal, decodes the command, generates a column access mode instruction signal, and activates a column address activation signal when the internal clock signal rises. An internal column address signal generating circuit generates an internal column address signal from an externally supplied address signal according to the column address activation signal. Accordingly, the internal column address is generated at an advanced timing to enable a following column selecting operation to be started at a faster timing. A synchronous semiconductor memory device capable of performing the column selecting operation at a high speed is thus provided.

Abstract: A reference voltage generating circuit having a fuse for controlling resistance includes a burn-in circuit for supplying burn-in voltage between opposite terminals of the fuse when a control signal is inputted to the burn-in circuit.

Abstract: A command decoder receives an externally supplied command independently of an internal clock signal, decodes the command, generates a column access mode instruction signal, and activates a column address activation signal when the internal clock signal rises. An internal column address signal generating circuit generates an internal column address signal from an externally supplied address signal according to the column address activation signal. Accordingly, the internal column address is generated at an advanced timing to enable a following column selecting operation to be started at a faster timing. A synchronous semiconductor memory device capable of performing the column selecting operation at a high speed is thus provided.

Abstract: A command decoder receives an externally supplied command independently of an internal clock signal, decodes the command, generates a column access mode instruction signal, and activates a column address activation signal when the internal clock signal uses. An internal column address signal generating circuit generates an internal column address signal from an externally supplied address signal according to the column address activation signal. Accordingly, the internal column address is generated at an advanced timing to enable a following column selecting operation to be started at a faster timing. A synchronous semiconductor memory device capable of performing the column selecting operation at a high speed is thus provided.

Abstract: An output buffer includes an NAND circuit, a first N channel MOS transistor connected between a power supply node and an output node, a second N channel MOS transistor connected between the output node and a ground node, the first to third drive circuits, and a delay circuit. The power supply voltage is first supplied to the gate of the second N channel MOS transistor by the second drive circuit. After a delay time delayed by the delay circuit has passed, boosted voltage is supplied to the gate of the second N channel MOS transistor by the third drive circuit. Accordingly, the output buffer is not influenced by the ringing and the pull-down characteristic improves.

Abstract: A semiconductor memory device is provided which can apply a voltage stress to every adjacent bit lines even when data is written using a data bit compression function in a burn-in test mode. More specifically, when data is written using the data bit compression function in the test mode, an input buffer circuit is brought to a state in which it receives a signal corresponding to a signal dq0 applied to a specific input/output terminal by a switch circuit controlled by a test mode specify signal TE in common. When an inversion designate signal INV is in an active state, a complementary signal corresponding to a signal obtained by inversion of signal dq0 by an inverting circuit is output to internal data buses IO0, ZIO0, and IO2, ZIO2. On the other hand, a complementary signal corresponding to signal dq0 is output to internal data buses IO1, ZIO1, and IO3, ZIO3.

Abstract: A voltage generation circuit has a charge pump circuit, a clamping circuit for clamping an output voltage of the charge pump circuit, and detecting means for detecting the output voltage of the charge pump circuit and supplying a control signal for boosting the output voltage to the charge pump circuit when the detected output voltage is lower than a reference voltage, wherein the detecting means includes a circuit for stopping supply of a control signal. This circuit stops supply of the control signal to the charge pump circuit when the clamping circuit is in operation.

Abstract: A ring oscillator according to the invention includes a plurality of inverters cascade-connected between an input node and an output node. Each inverter includes four transistors connected in series between a power supply node and a ground node. A first pair of transistors each have a channel sized to have an input capacitance for delaying the signal of a preceding stage inverter for a prescribed time period. A second pair of transistors are coupled to a current mirror circuit and limits current flowing through the first pair of transistors. Thus, power consumption for obtaining a signal in a prescribed cycle is reduced.