Patents by Inventor Motomu Kosuda
Motomu Kosuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10378100Abstract: Disclosed is a sputtering apparatus having a target (2) disposed offset with respect to a substrate (7), wherein the uniformity of a deposition amount can be ensured even when a substrate support holder (6) has a low number of rotations of several rotations to several tens of rotations and the amount of deposition is extremely small to provide such a film thickness of 1 nm or less.Type: GrantFiled: December 18, 2014Date of Patent: August 13, 2019Assignee: CANON ANELVA CORPORATIONInventors: Nobuo Yamaguchi, Koji Tsunekawa, Naoki Watanabe, Motomu Kosuda
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Publication number: 20150101927Abstract: Disclosed is a sputtering apparatus having a target (2) disposed offset with respect to a substrate (7), wherein the uniformity of a deposition amount can be ensured even when a substrate support holder (6) has a low number of rotations of several rotations to several tens of rotations and the amount of deposition is extremely small to provide such a film thickness of 1 nm or less.Type: ApplicationFiled: December 18, 2014Publication date: April 16, 2015Inventors: Nobuo YAMAGUCHI, Koji TSUNEKAWA, Naoki WATANABE, Motomu KOSUDA
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Patent number: 8415753Abstract: This invention provides a semiconductor device having a field effect transistor comprising a gate electrode comprising a metal nitride layer and a polycrystalline silicon layer, and the gate electrode is excellent in thermal stability and realizes a desired work function. In the semiconductor device, a gate insulating film 6 on a silicon substrate 5 has a high-permittivity insulating film formed of a metal oxide, a metal silicate, a metal oxide introduced with nitrogen, or a metal silicate introduced with nitrogen, the gate electrode has a first metal nitride layer 7 provided on the gate insulating film 6 and containing Ti and N, a second metal nitride layer 8 containing Ti and N, and a polycrystalline silicon layer 9, in the first metal nitride layer 7, a molar ratio between Ti and N (N/Ti) is not less than 1.1, and a crystalline orientation X1 is 1.1<X1 <1.8, and in the second metal nitride layer 8, the molar ratio between Ti and N (N/Ti) is not less than 1.1, and a crystalline orientation X2 is 1.Type: GrantFiled: April 28, 2010Date of Patent: April 9, 2013Assignee: Canon Anelva CorporationInventors: Takashi Nakagawa, Naomu Kitano, Kazuaki Matsuo, Motomu Kosuda, Toru Tatsumi
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Publication number: 20120199919Abstract: A gate electrode achieves a desired work function in a semiconductor device including a field-effect transistor equipped with a gate electrode composed of a metal nitride layer. The semiconductor device includes a silicon substrate and a field-effect transistor provided on the silicon substrate and having a gate insulating film and a gate electrode provided on the gate insulating film. The gate insulating film includes a high-permittivity insulating film formed of a metal oxide, a metal silicate, a metal oxide introduced with nitrogen, or a metal silicate introduced with nitrogen, and the gate electrode includes at least a metal nitride layer containing Ti and N. At least a part which is in contact with the gate insulating film of the metal nitride layer has a molar ratio between Ti and N (N/Ti ratio) of not less than 1.15 and a film density of not less than 4.7 g/cc.Type: ApplicationFiled: July 29, 2010Publication date: August 9, 2012Applicant: CANON ANELVA CORPORATIONInventors: Takashi Nakagawa, Naomu Kitano, Kazuaki Matsuo, Motomu Kosuda, Toru Tatsumi
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Publication number: 20120043617Abstract: This invention provides a semiconductor device having a field effect transistor comprising agate electrode comprising a metal nitride layer and a polycrystalline silicon layer, and the gate electrode is excellent in thermal stability and realizes a desired work function. In the semiconductor device, a gate insulating film 6 on a silicon substrate 5 has a high-permittivity insulating film formed of a metal oxide, a metal silicate, a metal oxide introduced with nitrogen, or a metal silicate introduced with nitrogen, the gate electrode has a first metal nitride layer 7 provided on the gate insulating film 6 and containing Ti and N, a second metal nitride layer 8 containing Ti and N, and a polycrystalline silicon layer 9, in the first metal nitride layer 7, a molar ratio between Ti and N (N/Ti) is not less than 1.1, and a crystalline orientation X1 is 1.1<X1<1.8, and in the second metal nitride layer 8, the molar ratio between Ti and N (N/Ti) is not less than 1.1, and a crystalline orientation X2 is 1.Type: ApplicationFiled: April 28, 2010Publication date: February 23, 2012Applicant: CANON ANELVA CORPORATIONInventors: Takashi Nakagawa, Naomu Kitano, Kazuaki Matsuo, Motomu Kosuda, Toru Tatsumi
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Patent number: 8088678Abstract: A first aspect of the present invention provides a semiconductor manufacturing apparatus including: a load lock chamber; a transfer chamber; and a treatment chamber 1 and a treatment chamber 2 which carry out treatment using plasma, wherein, in the treatment chamber 2, an exhaust means is provided with a control means for making an oxygen partial pressure into 1*10?5 [Pa] or less.Type: GrantFiled: December 4, 2009Date of Patent: January 3, 2012Assignee: Canon Anelva CorporationInventors: Naomu Kitano, Takashi Minami, Motomu Kosuda, Heiji Watanabe
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Patent number: 8026143Abstract: The object of the present invention is to provide a method of manufacturing high permittivity gate dielectrics for a device such as an MOSFET. A HfSiO film is formed by sputtering a Hf metal film on a SiO2 film (or a SiON film) on a Si wafer. A TiO2 film is formed by sputtering a Ti metal film on the HfSiO film and subjecting the Ti metal film to a thermal oxidation treatment. A TiN metal film is deposited on the TiO2 film. The series of treatments are performed continuously, without exposing the films and the wafer to atmospheric air. The resultant TiN/TiO2/HfSiO/SiO2/Si structure satisfies the conditions: EOT<1.0 nm, low leakage current, and hysteresis <20 mV.Type: GrantFiled: November 1, 2007Date of Patent: September 27, 2011Assignee: Canon Anelva CorporationInventors: Naomu Kitano, Takashi Minami, Motomu Kosuda, Heiji Watanabe
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Publication number: 20110042209Abstract: Disclosed is a sputtering device wherein a target (2) is disposed offset with respect to a substrate (7), wherein said sputtering device can ensure a uniform amount of deposition, even when a substrate support holder (6) has a low number of rotations of several rotations to several tens of rotations, and the amount of deposition is extremely small, such as a film thickness of 1 nm or less.Type: ApplicationFiled: June 16, 2009Publication date: February 24, 2011Applicant: CANON ANELVA CORPORATIONInventors: Nobuo Yamaguchi, Koji Tsunekawa, Naoki Watanabe, Motomu Kosuda
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Patent number: 7857946Abstract: A sputtering film forming method. which positions a target 4 and 5 at an incline to a surface of a substrate 10 whereupon a film is to be formed, and forms the film upon the surface of the substrate 10 whereupon the film is to be formed in an incline direction while the substrate 10 is rotated about a normal axis, terminates the forming of the film at a predetermined timing from the commencement of the forming of the film, wherein the forming of the film is terminated, when the substrate has rotated by 360 degrees×n+180 degrees+?, where n is a natural number, including 0, and ?10 degrees<?<10 degrees.Type: GrantFiled: April 16, 2008Date of Patent: December 28, 2010Assignee: Canon Anelva CorporationInventors: Naomu Kitano, Naoki Yamada, Takaaki Tsunoda, Nobuo Yamaguchi, Motomu Kosuda
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Publication number: 20100120238Abstract: A first aspect of the present invention provides a semiconductor manufacturing apparatus including: a load lock chamber; a transfer chamber; and a treatment chamber 1 and a treatment chamber 2 which carry out treatment using plasma, wherein, in the treatment chamber 2, an exhaust means is provided with a control means for making an oxygen partial pressure into 1*10?5 [Pa] or less.Type: ApplicationFiled: December 4, 2009Publication date: May 13, 2010Applicant: CANON ANELVA CORPORATIONInventors: Naomu Kitano, Takashi Minami, Motomu Kosuda, Heiji Watanabe
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Patent number: 7655549Abstract: A method to improve a high-k dielectric film and metal gate interface in the fabrication of a MOSFET by depositing a metal gate on a high-k dielectric, the method includes annealing a substrate with a high-k dielectric film deposited thereon in a thermal annealing module and depositing a metal gate material on the annealed substrate in a metal gate deposition module, wherein the annealing step and the depositing step are carried out consecutively without a vacuum break.Type: GrantFiled: February 6, 2006Date of Patent: February 2, 2010Assignee: Canon Anelva CorporationInventors: Wickramanayaka Sunil, Motomu Kosuda, Naoki Yamada, Naomu Kitano
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Publication number: 20090178621Abstract: An apparatus to improve high-k dielectric film and metal gate interface in the fabrication of MOSFET by depositing a metal gate on a high-k dielectric comprising an annealing step annealing a substrate with high-k dielectric film deposited thereon in a thermal annealing module and a depositing step depositing a metal gate material on said annealed substrate in a metal gate deposition module, characterized that said annealing step and depositing step are carried out consecutively without a vacuum break.Type: ApplicationFiled: March 9, 2009Publication date: July 16, 2009Applicant: CANON ANELVA CORPORATIONInventors: Wickramanayaka Sunil, Motomu Kosuda, Naoki Yamada, Naomu Kitano
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Publication number: 20090170300Abstract: The object of the present invention is to provide a method of manufacturing high permittivity gate dielectrics for a device such as an MOSFET. A HfSiO film 104 is formed by sputtering a Hf metal film 103 on a SiO2 film (or a SiON film) 102 on a Si wafer 101. A TiO2 film 106 is formed by sputtering a Ti metal film 105 on the HfSiO film 104 and subjecting the Ti metal film 105 to a thermal oxidation treatment. A TiN metal film 107 is deposited on the TiO2 film 106. The series of treatments are performed continuously, without exposing the films and the wafer to atmospheric air. The resultant TiN/TiO2/HfSiO/SiO2/Si structure satisfies the conditions: EOT<1.0 nm, low leakage current, and hysteresis<20 mV.Type: ApplicationFiled: February 27, 2009Publication date: July 2, 2009Applicant: CANON ANELVA CORPORATIONInventors: Naomu Kitano, Takashi Minami, Motomu Kosuda, Heiji Watanabe
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Publication number: 20080305597Abstract: The object of the present invention is to provide a method of manufacturing high permittivity gate dielectrics for a device such as an MOSFET. A HfSiO film 104 is formed by sputtering a Hf metal film 103 on a SiO2 film (or a SiON film) 102 on a Si wafer 101. A TiO2 film 106 is formed by sputtering a Ti metal film 105 on the HfSiO film 104 and subjecting the Ti metal film 105 to a thermal oxidation treatment. A TiN metal film 107 is deposited on the TiO2 film 106. The series of treatments are performed continuously, without exposing the films and the wafer to atmospheric air. The resultant TiN/TiO2/HfSiO/SiO2/Si structure satisfies the conditions: EOT<1.0 nm, low leakage current, and hysteresis<20 mV.Type: ApplicationFiled: November 1, 2007Publication date: December 11, 2008Applicant: CANON ANELVA CORPORATIONInventors: Naomu Kitano, Takashi Minami, Motomu Kosuda, Heiji Watanabe
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Publication number: 20080264775Abstract: A sputtering film forming method. which positions a target 4 and 5 at an incline to a surface of a substrate 10 whereupon a film is to be formed, and forms the film upon the surface of the substrate 10 whereupon the film is to be formed in an incline direction while the substrate 10 is rotated about a normal axis, terminates the forming of the film at a predetermined timing from the commencement of the forming of the film, wherein the forming of the film is terminated, when the substrate has rotated by 360 degrees×n+180 degrees+?, where n is a natural number, including 0, and ?10 degrees<?<10 degrees.Type: ApplicationFiled: April 16, 2008Publication date: October 30, 2008Applicant: CANON ANELVA CORPORATIONInventors: Naomu Kitano, Naoki Yamada, Takaaki Tsunoda, Nobuo Yamaguchi, Motomu Kosuda
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Publication number: 20060194396Abstract: A method to improve a high-k dielectric film and metal gate interface in the fabrication of a MOSFET by depositing a metal gate on a high-k dielectric, the method includes annealing a substrate with a high-k dielectric film deposited thereon in a thermal annealing module and depositing a metal gate material on the annealed substrate in a metal gate deposition module, wherein the annealing step and the depositing step are carried out consecutively without a vacuum break.Type: ApplicationFiled: February 6, 2006Publication date: August 31, 2006Applicant: CANON ANELVA CORPORATIONInventors: Wickramanayaka Sunil, Motomu Kosuda, Naoki Yamada, Naomu Kitano