Abstract: In a correlation arithmetic system adapted to detect a relative difference between two functions, an operation is simplified. This makes it possible to perform the operation with a small scale of hardware and also with great accuracy. There is adopted an operation g*h instead of the “product” in the correlation arithmetic operation. There is disclosed an arithmetic unit in which two numeral values a and b are inputted, and the two numerical values a and b are subjected to a predetermined operation process, so that a numerical value c representative of an operation result is derived. The arithmetic unit has an absolute value operation unit for evaluating an absolute value |c| of the numerical value c, and a sign operation unit for evaluating a sign “sing (c)” of the numerical value c.

Abstract: In a correlation arithmetic system adapted to detect a relative difference between two functions, an operation is simplified. This makes it possible to perform the operation with a small scale of hardware and also with great accuracy. There is adopted an operation g*h instead of the “product” in the correlation arithmetic operation. There is disclosed an arithmetic unit in which two numeral values a and b are inputted, and the two numerical values a and b are subjected to a predetermined operation process, so that a numerical value c representative of an operation result is derived. The arithmetic unit has an absolute value operation unit for evaluating an absolute value |c| of the numerical value c, and a sign operation unit for evaluating a sign “sign (c)” of the numerical value c.

Abstract: In a correlation arithmetic system adapted to detect a relative difference between two functions, an operation is simplified. This makes it possible to perform the operation with a small scale of hardware and also with great accuracy. There is adopted an operation g*h instead of the "product" in the correlation arithmetic operation. There is disclosed an arithmetic unit in which two numeral values a and b are inputted, and the two numerical values a and b are subjected to a predetermined operation process, so that a numerical value c representative of an operation result is derived. The arithmetic unit has an absolute value operation unit for evaluating an absolute value .vertline.c.vertline. of the numerical value c, and a sign operation unit for evaluating a sign "sing (c)" of the numerical value c.

Abstract: In a correlation arithmetic system adapted to detect a relative difference between two functions, an operation is simplified. This makes it possible to perform the operation with a small scale of hardware and also with great accuracy. There is adopted an operation g*h instead of the "product" in the correlation arithmetic operation. There is disclosed an arithmetic unit in which two numeral values a and b are inputted, and the two numerical values a and b are subjected to a predetermined operation process, so that a numerical value c representative of an operation result is derived. The arithmetic unit has an absolute value operation unit for evaluating an absolute value .vertline.c.vertline. of the numerical value c, and a sign operation unit for evaluating a sign "sign (c)" of the numerical value c.

Abstract: A data processing circuit adapted for use in pattern matching between two sets of multi-dimensional signal data. The data processing circuit performs integration-based conversion on data aw calculated by multiplying first multi-dimensional signal data a by a window function w, second multi-dimensional signal data b, data b.sup.2 calculated by squaring the data b, and the window function w, calculates a correlation between the first and second multi-dimensional signal data items a and b on the basis of the data aw and data b subjected to integration-based conversion, calculates a means of deviations from the square of the second multi-dimensional signal data b on the basis of the data b.sup.2 and window function subjected to integration-based conversion, and calculates a portion of the second multi-dimensional signal data b most consistent with the first multi-dimensional signal data a multiplied by the window function w.

Abstract: In a correlation arithmetic system adapted to detect a relative difference between two functions, an operation is simplified. This makes it possible to perform the operation with a small scale of hardware and also with great accuracy. There is adopted an operation g*h instead of the "product" in the correlation arithmetic operation. There is disclosed an arithmetic unit in which two numeral values a and b are inputted, and the two numerical values a and b are subjected to a predetermined operation process, so that a numerical value c representative of an operation result is derived. The arithmetic unit has an absolute value operation unit for evaluating an absolute value .vertline.c.vertline. of the numerical value c, and a sign operation unit for evaluating a sign "sign (c)" of the numerical value c.

Abstract: There are provided n operation circuits in a multiple-valued logic circuit which receives plural multiple-valued input logic signals corresponding to respective numeral values and outputs a multiple-valued output logic signal corresponding to a sum of the respective numeral values. The kth operation circuit includes multiple-input comparators generating carry signals, and multiple-input amplifiers performing weighted linear voltage adding operations on input signals at the kth digit, carry signals of the input signals at the kth digit, and carry signals from the (k-1)th digit where k is 0, 1, 2, . . . , n-1. The multiple-input amplifier has a feedback circuit having a capacitance. The multiple-input comparator and the multiple-input amplifier are connected to corresponding input signals through capacitances. A voltage gain of the multiple-input amplifier is based on a ratio of the capacitance through which the input signal is applied and the capacitance of the feedback circuit.

Abstract: A hetero-bipolar transistor includes a collector layer of a first conductivity type, a base layer of a second conductivity type provided on the collector layer, a first emitter structure of the first conductivity type provided on the base layer, and a second emitter structure of the first conductivity type and provided on the base layer, wherein the first and second emitter structures are doped with respect to the base layer, with a sufficiently high impurity concentration level such that a Zener breakdown occurs at the p-n junction formed between the base layer and the first or second emitters upon application of a reverse bias voltage.

Abstract: A basic logic circuit 10 which functions as a data selector consists of a basic circuit 11, a HET (hot electron transistor) 12, the first and second emitters of which are connected to the first emitter of a HET 16 and a data input end A respectively, and an inverter 13 connected to an output end of the circuit 11. In a HET 14 having no base electrode, its collector is connected to a power supply line VCC via a load resistor 15, its first emitter is used exclusively for current output by connecting to the collector of the HET 16 the second emitter of which is connected to a power supply line VSS, its second emitter is used for current input/output by directly connected to a control input end S, and its third emitter is used exclusively for current input by connecting to the first emitter of a HET 17 the second emitter of which is connected to a data input end B. An output data Q is equal to an input data A/B when a control data S is high/low level respectively.

Abstract: A sequential logic circuit includes N state hold circuit where N is an integer. Each of the state hold circuits has a first input terminal, a second input terminal and an output terminal. The state hold circuits are cascaded via the respective first input terminals. The second input terminals of the state hold circuits receive a first clock signal. The first input terminal of one of the state hold circuits in a first stage receives a data signal. The output signal is obtained via the output terminal of one of the state hold circuits in a final stage.

Abstract: A logic circuit including a transistor having a control electrode connected to three input terminals at which are received three respective input signals, each having, selectively, either a high or a low voltage level, and first and second electrodes, one thereof connected to a first power supply potential and the other thereof connected through a diode having N-type negative differential resistance to a second, lower power supply potential. An output terminal is connected to one of the first and second electrodes of the transistor for deriving an output signal.

Abstract: A logic circuit first, second and third input terminals, an output terminal, a load resistance element, and a transistor having a negative differential conductance. The collector is connected to the output terminal and coupled to a first power source via the load resistance element. The emitter is connected to a second power source. First, second and third resistors are connected between the base of the transistor and the first, second and third input terminals, respectively. A fourth resistor is connected between the base and emitter of the transistor.

Abstract: A sequential logic circuit includes first, second and third state hold circuits, each having a first input terminal, a second input terminal and an output terminal. The first input terminal of the first state hold circuit receives a clock signal, and the second input terminal of the first state hold circuit and the first input terminal of the second state hold circuit receive a data signal. The second input terminal of the second state hold circuit receives an inverted clock signal corresponding to an inverted version of the clock signal. The output terminal of the first state hold circuit and the output terminal of the second state hold circuit are connected to the first and second input terminals of the third state hold circuit, respectively. An output signal of the sequential logic circuit is output via the output terminal of the third state hold circuit.

Abstract: A logic circuit includes n input terminals where n is an odd integer, an output terminal, and n input resistance elements respectively connected to the n input terminals. The logic circuit also includes a negative differential conductance element having a negative differential conductance in which the negative differential conductance element outputs a peak voltage and a valley voltage higher than the peak voltage. The negative differential conductance element has a first terminal coupled to the n input terminals via the n input resistance elements, and a second terminal.

Abstract: A status holding circuit includes a transistor having an emitter coupled to a negative power source, a collector and a base coupled to said collector and having a negative conductance range, first and second input terminals to which first and second input signals are applied, a first resistor provided between said first input terminal and the collector of said transistor, a second resistor provided between said second input terminal and the collector of said transistor, and an amplifier provided between a positive power source and said negative power source, for amplifying an output of said transistor drawn from said base thereof to thereby generate an amplified output signal.