Patents by Inventor Mototada Sakashita
Mototada Sakashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11276442Abstract: Apparatuses and methods for clock leveling in semiconductor memory are disclosed. In an example apparatus, a latency control circuit is configured to provide in first and second modes an active first control signal having a timing based on latency information and a system clock. A clock leveling control circuit is configured to provide in the first mode an active second control signal responsive to an active first control signal at a clock transition of a first clock and further configured to provide in the second mode clock leveling feedback responsive to the active first control signal at a transition of a second clock. A read clock circuit is configured to provide the multiphase clocks responsive to the active second control signal. A serializer circuit configured to serialize the data based on the multiphase clocks from the read clock circuit to provide the data in series.Type: GrantFiled: November 13, 2020Date of Patent: March 15, 2022Assignee: Micron Technology, Inc.Inventors: Koji Ito, Keisuke Tada, Mototada Sakashita
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Publication number: 20210151087Abstract: Apparatuses and methods for clock leveling in semiconductor memory are disclosed. In an example apparatus, a latency control circuit is configured to provide in first and second modes an active first control signal having a timing based on latency information and a system clock. A clock leveling control circuit is configured to provide in the first mode an active second control signal responsive to an active first control signal at a clock transition of a first clock and further configured to provide in the second mode clock leveling feedback responsive to the active first control signal at a transition of a second clock. A read clock circuit is configured to provide the multiphase clocks responsive to the active second control signal. A serializer circuit configured to serialize the data based on the multiphase clocks from the read clock circuit to provide the data in series.Type: ApplicationFiled: November 13, 2020Publication date: May 20, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Koji Ito, Keisuke Tada, Mototada Sakashita
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Patent number: 10839876Abstract: Apparatuses and methods for clock leveling in semiconductor memory are disclosed. In an example apparatus, a latency control circuit is configured to provide in first and second modes an active first control signal having a timing based on latency information and a system clock. A clock leveling control circuit is configured to provide in the first mode an active second control signal responsive to an active first control signal at a clock transition of a first clock and further configured to provide in the second mode clock leveling feedback responsive to the active first control signal at a transition of a second clock. A read clock circuit is configured to provide the multiphase clocks responsive to the active second control signal. A serializer circuit configured to serialize the data based on the multiphase clocks from the read clock circuit to provide the data in series.Type: GrantFiled: November 15, 2019Date of Patent: November 17, 2020Assignee: Micron Technology, Inc.Inventors: Koji Ito, Keisuke Tada, Mototada Sakashita
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Patent number: 9030245Abstract: Disclosed herein is a semiconductor device that includes: a measurement circuit which measures propagation time of an internal clock signal; a delay adjustment circuit which adjusts the propagation time of the internal clock signal on the basis of a result of measurement by the measurement circuit; and a data output circuit which outputs a data signal in synchronization with the internal clock signal.Type: GrantFiled: December 21, 2012Date of Patent: May 12, 2015Assignee: PS4 Luxco S.A.R.L.Inventors: Mototada Sakashita, Satoshi Morishita, Yoshinori Matsui, Yasushi Matsubara
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Patent number: 8787089Abstract: An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. One embodiment of the invention also provides a method of controlling the semiconductor device.Type: GrantFiled: December 3, 2012Date of Patent: July 22, 2014Assignee: Spansion LLCInventors: Masaru Yano, Kazuhide Kurosaki, Mototada Sakashita
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Patent number: 8325523Abstract: An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. One embodiment of the invention also provides a method of controlling the semiconductor device.Type: GrantFiled: August 1, 2011Date of Patent: December 4, 2012Assignee: Spansion LLCInventors: Masaru Yano, Kazuhide Kurosaki, Mototada Sakashita
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Publication number: 20110286273Abstract: An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. One embodiment of the invention also provides a method of controlling the semiconductor device.Type: ApplicationFiled: August 1, 2011Publication date: November 24, 2011Inventors: Masaru YANO, Kazuhide KUROSAKI, Mototada SAKASHITA
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Patent number: 8018767Abstract: The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. The present invention also provides a method of controlling the semiconductor device.Type: GrantFiled: November 20, 2008Date of Patent: September 13, 2011Assignee: Spansion, LLCInventors: Masaru Yano, Kazuhide Kurosaki, Mototada Sakashita
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Publication number: 20090109757Abstract: The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. The present invention also provides a method of controlling the semiconductor device.Type: ApplicationFiled: November 20, 2008Publication date: April 30, 2009Inventors: Masaru Yano, Kazuhide Kurosaki, Mototada Sakashita
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Patent number: 7468909Abstract: The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. The present invention also provides a method of controlling the semiconductor device.Type: GrantFiled: December 11, 2006Date of Patent: December 23, 2008Assignee: Spansion LLCInventors: Masaru Yano, Kazuhide Kurosaki, Mototada Sakashita
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Patent number: 7450419Abstract: The present invention provides a semiconductor device and a method for controlling a semiconductor device having a memory cell array having a plurality of nonvolatile memory cells, the method including detecting the number of bits to be written as division data that is divided from data to be programmed into the memory cell array, comparing the number of bits with a predetermined number of bits, inverting or not inverting the division data to produce inversion data in accordance with a result of comparing the number of bits with the predetermined number of bits, and programming the inversion data into the memory cell array. The method further includes detecting the number of bits to be written as next division data and comparing the number of bits of next division data with the predetermined number of bits, while concurrently programming the inversion data into the memory cell array.Type: GrantFiled: December 7, 2006Date of Patent: November 11, 2008Assignee: Spansion LLCInventors: Mototada Sakashita, Masaru Yano, Akira Ogawa, Tsutomu Nakai
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Patent number: 7385844Abstract: A semiconductor device includes: a memory cell array that has a plurality of non-volatile memory cells each having a first bit and a second bit in different regions in a charge storing layer; an SRAM array (first memory unit) that stores data to be written into the memory cell array; a WR sense amplifier block (second memory unit) that stores first divided data to be written into the first bit and second divided data to be written into the second bit, the first divided data being formed by dividing the data into predetermined units, the second divided data being formed by dividing the data into predetermined units; and a control circuit that writes the second divided data into the first bit of the memory cells of the memory cell array (step S28) after writing the first divided data into the second bit of the memory cells of the memory cell array (step S22).Type: GrantFiled: July 27, 2006Date of Patent: June 10, 2008Assignee: Spansion LLCInventors: Masaru Yano, Hideki Arakawa, Mototada Sakashita
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Patent number: 7372743Abstract: A control method for a nonvolatile storage device having a storage mode in which in a memory cell provided with a trapping dielectric layer 1-bit data is stored depending on the presence or absence of charge in a first trapping region. In a dynamic reference cell initialization operation, a charge accumulation operation is performed, as a preset operation in the initialization operation, on second trapping regions of first and second dynamic reference cells to a charge accumulation operation on a second trapping region of the memory cell. In addition, at the time of data rewrite, preprogram verification and preprogramming are performed on the first trapping regions. This makes it possible to shorten the time taken for initialization and data rewrite.Type: GrantFiled: December 13, 2006Date of Patent: May 13, 2008Assignee: Spansion, LLCInventors: Masaru Yano, Hideki Arakawa, Mototada Sakashita, Akira Ogawa, Yoshiaki Shinmura, Hajime Aoki
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Patent number: 7362620Abstract: A semiconductor device (1) includes a non-volatile memory cell array (2), a write/read circuit (30) writing data into and reading data from the non-volatile memory cell array (2), a data input/output circuit (80), and a volatile memory cell array (40) including a first latch circuit (41) that is connected to the write/read circuit (30) and latches first data, and a second latch circuit (42) that is connected to the data input/output circuit (80) and latches second data. The device (1) may further include an inverter circuit (310) that inverts the first data in accordance with the number of bits to be actually written among the first data, and a control circuit (3) that causes the second data to be latched in the second latch circuit (42) while the first data is being written into the non-volatile memory cell array (2). This semiconductor device (1) has a shorter writing time and a smaller circuit area.Type: GrantFiled: March 31, 2006Date of Patent: April 22, 2008Assignee: Spansion LLCInventors: Masaru Yano, Hideki Arakawa, Mototada Sakashita
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Publication number: 20070183211Abstract: The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. The present invention also provides a method of controlling the semiconductor device.Type: ApplicationFiled: December 11, 2006Publication date: August 9, 2007Inventors: Masaru Yano, Kazuhide Kurosaki, Mototada Sakashita
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Publication number: 20070183193Abstract: A control method for a nonvolatile storage device having a storage mode in which in a memory cell provided with a trapping dielectric layer 1-bit data is stored depending on the presence or absence of charge in a first trapping region. In a dynamic reference cell initialization operation, a charge accumulation operation is performed, as a preset operation in the initialization operation, on second trapping regions of first and second dynamic reference cells to a charge accumulation operation on a second trapping region of the memory cell. In addition, at the time of data rewrite, preprogram verification and preprogramming are performed on the first trapping regions. This makes it possible to shorten the time taken for initialization and data rewrite.Type: ApplicationFiled: December 13, 2006Publication date: August 9, 2007Inventors: Masaru Yano, Hideki Arakawa, Mototada Sakashita, Akira Ogawa, Yoshiaki Shinmura, Hajime Aoki
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Publication number: 20070180184Abstract: The present invention provides a semiconductor device and a method for controlling a semiconductor device having a memory cell array having a plurality of nonvolatile memory cells, the method including detecting the number of bits to be written as division data that is divided from data to be programmed into the memory cell array, comparing the number of bits with a predetermined number of bits, inverting or not inverting the division data to produce inversion data in accordance with a result of comparing the number of bits with the predetermined number of bits, and programming the inversion data into the memory cell array. The method further includes detecting the number of bits to be written as next division data and comparing the number of bits of next division data with the predetermined number of bits, while concurrently programming the inversion data into the memory cell array.Type: ApplicationFiled: December 7, 2006Publication date: August 2, 2007Inventors: Mototada Sakashita, Masaru Yano, Akira Ogawa, Tsutomu Nakai
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Publication number: 20070025154Abstract: A semiconductor device includes: a memory cell array that has a plurality of non-volatile memory cells each having a first bit and a second bit in different regions in a charge storing layer; an SRAM array (first memory unit) that stores data to be written into the memory cell array; a WR sense amplifier block (second memory unit) that stores first divided data to be written into the first bit and second divided data to be written into the second bit, the first divided data being formed by dividing the data into predetermined units, the second divided data being formed by dividing the data into predetermined units; and a control circuit that writes the second divided data into the first bit of the memory cells of the memory cell array (step S28) after writing the first divided data into the second bit of the memory cells of the memory cell array (step S22).Type: ApplicationFiled: July 27, 2006Publication date: February 1, 2007Inventors: Masaru Yano, Hideki Arakawa, Mototada Sakashita
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Publication number: 20060245247Abstract: A semiconductor device (1) includes a non-volatile memory cell array (2), a write/read circuit (30) writing data into and reading data from the non-volatile memory cell array (2), a data input/output circuit (80), and a volatile memory cell array (40) including a first latch circuit (41) that is connected to the write/read circuit (30) and latches first data, and a second latch circuit (42) that is connected to the data input/output circuit (80) and latches second data. The device (1) may further include an inverter circuit (310) that inverts the first data in accordance with the number of bits to be actually written among the first data, and a control circuit (3) that causes the second data to be latched in the second latch circuit (42) while the first data is being written into the non-volatile memory cell array (2). This semiconductor device (1) has a shorter writing time and a smaller circuit area.Type: ApplicationFiled: March 31, 2006Publication date: November 2, 2006Inventors: Masaru Yano, Hideki Arakawa, Mototada Sakashita
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Patent number: 6768682Abstract: When data is programmed into nonvolatile memory cells, a programming voltage is applied, with increasing, to the memory cells a plurality of times. During this data programming, the increment of the programming voltage is set to a first voltage, which is maintained until the threshold voltages of all the memory cells to be programmed reach an initial value. Thereafter, the increment is set to a second voltage, which is maintained until the threshold voltages reach a target value. Increasing the programming voltage without varying the increment thereof allows the threshold voltages of the memory cells to approach the target value in a smaller number of times programmed. Additionally, setting the increment of the programming voltage to the second voltage after the threshold voltages exceed the initial value can minimize the deviation of the threshold voltages from the target value. Consequently, the programming time of the memory cells can be reduced.Type: GrantFiled: September 30, 2002Date of Patent: July 27, 2004Assignee: Fujitsu LimitedInventors: Masaru Yano, Mototada Sakashita