Abstract: A method reduces circuit data to be simulated, by extracting element data that influences a result of simulation out of the circuit data, thereby shortening a simulation time while maintaining the accuracy of simulation. Also provided is a simulation method that employs the reduction method. The method includes the steps of entering one of an input vector and/or an observation point for the circuit data to be simulated, and extracting an element data corresponding to a node influenced by propagation of a varying state of the input signal, the varying state for the node having an influence for the observation point, from the circuit data according to the input vector and/or observation point. The extracted nodes and elements related thereto are used to prepare reduced circuit data that is simulated. The method reduces the scale of a circuit to simulate by extracting only essential elements that affect a result of simulation from circuit data such as a netlist that forms the circuit to be simulated.

Abstract: In the timing analysis method, connection information is compared to circuit patterns that have been stored in a memory in advance after reading the connection information of an electrical circuit, a connection information supplement process to supplement vertically circuit connection information regarding the matched circuit pattern for the stored connection information is performed when the connection information is matched with one of the registered circuit patterns, and a timing analysis of the connection information that has been supplemented by the connection information supplement process is executed.

Abstract: The present invention provide a system and a method for analyzing the static timing for LSIs which involves rather a small number of false paths contained in output results and also which reduces the processing time required.

Abstract: A method, according to a hierarchical processing used for a computer-aided design system, for automatically wiring a circuit by dividing a region into a plurality of coarse global grids. The automatic wiring method includes the steps of: setting up and calculating an evaluation function having therein a plurality of evaluation terms for indicating selectability by which the cut-line is preferentially selected so that a wiring congestion is most relaxed; giving weights to the respective plurality of evaluation terms and defining an evaluation function which totals the plurality of the evaluation terms; dividing the region into two by a cut-line having a minimum value in the evaluation functions; determining a position to cross all nets crossing the cut-line; and performing the above steps recursively and hierarchically until the divided regions become a predetermined minimum size.

Abstract: A semiconductor integrated circuit device comprises a plurality of cell arrays including at least one cell array having main and one feed-through cells, and a plurality of clock driver cells provided on the cell arrays. The feed-through cells are selectively connected to the clock driver cells so that loads imposed to the clock driver cells are made substantially uniform.