Patents by Inventor Motoyoshi Komoda

Motoyoshi Komoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5398332
    Abstract: A system for detecting the malfunction of a CPU (Central Processing Unit) is disclosed. A watchdog timer applies an interrupt signal to the CPU on detecting the malfunction of the CPU. In response to the interrupt signal, the CPU executes interrupt processing to increment the number of times that the CPU has malfunctioned stored in a nonvolatile memory. As the number of times stored in the nonvolatile memory reaches a predetermined value, the CPU displays an alarm message on a display.
    Type: Grant
    Filed: July 17, 1992
    Date of Patent: March 14, 1995
    Assignee: NEC Corporation
    Inventors: Motoyoshi Komoda, Masahiro Ishigami
  • Patent number: 5332950
    Abstract: A driver circuit for a display device, in which first and second clock pulse generator circuits generate first and second clock pulses to a gate circuit for allowing the first clock pulse to pass when the first and second clock pulses are a high level, and by the output of the gate circuit, a combination of a transistor and an inductance generate a high voltage pulse. The high voltage pulse is rectified in a triple voltage rectifying circuit to output a high voltage output for driving the display device such as EL elements, and the high voltage output can be reset by a low frequency pulse output from a discharge circuit. As a result, no inverter is required, and a small-sized and light-weighted driver circuit is achieved with a long luminescence life of the EL elements and without noises offensive to the ear.
    Type: Grant
    Filed: September 25, 1992
    Date of Patent: July 26, 1994
    Assignee: NEC Corporation
    Inventors: Motoyoshi Komoda, Minoru Katsumata
  • Patent number: 5323457
    Abstract: A white noise suppressing circuit for suppressing white noise contained in a received voice of a speaker telephone apparatus includes a filter for suppressing white noise contained in an aural input signal input to an aural signal line, a switch for short-circuiting the filter, a detecting circuit for detecting the aural input signal, and a comparator for comparing an output of the detecting circuit with a preset voltage and for controlling the switch on the basis of the results of the comparison. When it is determined by the comparator that there is a voice input, the switch is short-circuited to make the filter inoperable. When there is no voice input, the switch is opened so as to make the filter operate.
    Type: Grant
    Filed: January 17, 1992
    Date of Patent: June 21, 1994
    Assignee: NEC Corporation
    Inventors: Tatsuji Ehara, Motoyoshi Komoda, Akimasa Matsushita
  • Patent number: 5212810
    Abstract: Terminal equipment having transmitting and receiving functions for a vehicle radio telephone system has a function thereof limited to one of a plurality of modes depending on the time zone. The equipment is automatically locked when a predetermined period of time expires after the end of a communication. The area wherein a call can be originated on the equipment is limited to one of local, domestic and international areas on the basis of the time zone. A memory has a plurality of addresses each being loaded with a particular telephone number to allow the single equipment to selectively use a plurality of telephone channels, on the basis of the time zone. A plurality of memories each stores a particular speed call number table or a particular unattended telephone message table, so that the tables are selectively used depending on the time zone.
    Type: Grant
    Filed: June 15, 1990
    Date of Patent: May 18, 1993
    Assignee: NEC Corporation
    Inventors: Koji Maeda, Yutaka Tomiyori, Shinji Kawamura, Motoyoshi Komoda, Shinobu Okuno, Hiroshi Takizawa
  • Patent number: 5179723
    Abstract: In a mobile telephone device (10) comprising a serial interface (13b) and subjectable to an aging operation with an aging device (20) connected to the serial interface, a central processing unit (12) delivers a clock signal to an aging jig (25) through an interface unit (13) and the serial interface. In synchronism with the clock signal, the aging jig supplies particular data to the central processing unit through the interface unit and the serial interface. The central processing unit receives serial data supplied to the serial interface as received data in synchronism with the clock signal. The serial data is supplied to the serial interface both during progress of the aging operation and while the mobile telephone device is not subjected to the aging operation. The central processing unit judges whether or not the received data coincides with the particular data. When the received data coincides with the particular data, the central processing unit carries out the aging operation.
    Type: Grant
    Filed: June 6, 1990
    Date of Patent: January 12, 1993
    Assignee: NEC Corporation
    Inventor: Motoyoshi Komoda
  • Patent number: 5101178
    Abstract: Frequency compensation for a crystal oscillator circuit whose oscillation frequency is dependent on source voltage applied thereto. When a capacitor is added to the frequency compensation terminal of the crystal oscillator circuit, the circuit changes the oscillation frequency thereof on the basis of the capacitance of the capacitor. A source voltage detector compares the source voltage being applied to the crystal oscillator circuit with a predetermined reference voltage and produces a control signal matching whether the source voltage is higher or lower than the reference voltage. On receiving the control signal, a control switch turns on or off the contact thereof to add or not to add the capacitor to the frequency compensation terminal.
    Type: Grant
    Filed: March 26, 1991
    Date of Patent: March 31, 1992
    Assignee: NEC Corporation
    Inventor: Motoyoshi Komoda
  • Patent number: 4982443
    Abstract: An instantaneous voltage drop detector includes a reset signal generating circuit which generates a low-level reset signal when a DC power voltage falls below a predetermined level. When the reset signal exists, an integrating circuit discharges the electric charge charged thereon in accordance with its time constant. If the reset signal disappears, i.e., the output of the reset signal generating circuit changes to a high level, a changing circuit rapidly charges the integrating circuit to avoid interference between instantaneous voltage drops which continuously occur at a short interval. The detector also includes a comparator which compares the output level of the integrating circuit with a reference level and a latch circuit (E/F) which latches the output of the comparator in response to the disappearance of the reset signal, i.e., in response to the positive-going edge of output of the reset signal generating circuit.
    Type: Grant
    Filed: December 28, 1988
    Date of Patent: January 1, 1991
    Assignee: NEC Corporation
    Inventor: Motoyoshi Komoda