Patents by Inventor Motoyuki Tanisho

Motoyuki Tanisho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11088960
    Abstract: An information processing apparatus includes a processor that obtains a flow table from a switch apparatus that processes packets by using the flow table. The processor creates, for each flow registered with the flow table, a verification packet based on identification information that identifies each flow. The processor determines a number of verification packets based on a count value that represents a number of actual packets that have arrived at the switch apparatus. The processor generates the number of verification packets for each flow by copying the verification packet created for each flow. The processor determines transmission order of the generated verification packets based on the count value for each flow and time information that represents a time when a final actual packet of each flow has arrived at the switch apparatus.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: August 10, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Motoyuki Tanisho
  • Publication number: 20190356605
    Abstract: An information processing apparatus includes a processor that obtains a flow table from a switch apparatus that processes packets by using the flow table. The processor creates, for each flow registered with the flow table, a verification packet based on identification information that identifies each flow. The processor determines a number of verification packets based on a count value that represents a number of actual packets that have arrived at the switch apparatus. The processor generates the number of verification packets for each flow by copying the verification packet created for each flow. The processor determines transmission order of the generated verification packets based on the count value for each flow and time information that represents a time when a final actual packet of each flow has arrived at the switch apparatus.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 21, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Motoyuki Tanisho
  • Patent number: 10015076
    Abstract: A managing unit adds update information to an entry to be updated of a table updated prior to a change of a network configuration, and deletes the update information when the update of the table caused by the change of the network configuration is completed. A packet processing unit executes a plurality of pipeline processes using the table sequentially, and suspends executing the pipeline processes when the update information is added to any entry of the table. A reprocessing control unit stores an input packet in a reprocessing queue when the pipeline processes executed by the packet processing unit is suspended, and transfers the packet stored in the reprocessing queue to the input queue when update of the table to which the update information is added is all completed.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: July 3, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Yasutaka Kanayama, Motoyuki Tanisho
  • Publication number: 20170373928
    Abstract: A server detects an abnormality of a VM being a transfer destination of a packet; rewrites, when the VM is switched, a first relationship between a transfer destination MAC address and a port number of the VM before switching to a first relationship between the MAC address and a port number of the switched VM; decides, from the port number being matched based on the rewritten first relationship and a second relationship among a port number of the switched VM, a transfer destination MAC address, and a transfer destination IP address, the transfer destination MAC address and the transfer destination IP address of the switched VM; rewrites the transfer destination MAC address and the transfer destination IP address included in the header of the packet received from a network to the decided MAC address and the IP address; and transfers the rewritten packet to the switched VM.
    Type: Application
    Filed: May 25, 2017
    Publication date: December 28, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Yusuke UJIIE, Motoyuki Tanisho, Tetsuo EHARA
  • Patent number: 9626469
    Abstract: An information processing apparatus includes a processor and a memory configured to store therein correspondence information defining an association relationship between position of the connection point of circuits and information of wiring which has one end located at the position of the connection point. The processor is configured to identify a first circuit from a group of multiple images representing an overall circuit, acquire, based on the correspondence information, information of a first position of a connection point of a second circuit at which the identified first circuit is coupled and information of a first wiring which one end is located at the first position, extract, from the second image, a partial image that includes images of the first wiring and the connection point at the first position based on the acquired information of the first position and the first wiring, and output the extracted partial image.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: April 18, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shuichiro Yamada, Motoyuki Tanisho
  • Publication number: 20170012855
    Abstract: A managing unit adds update information to an entry to be updated of a table updated prior to a change of a network configuration, and deletes the update information when the update of the table caused by the change of the network configuration is completed. A packet processing unit executes a plurality of pipeline processes using the table sequentially, and suspends executing the pipeline processes when the update information is added to any entry of the table. A reprocessing control unit stores an input packet in a reprocessing queue when the pipeline processes executed by the packet processing unit is suspended, and transfers the packet stored in the reprocessing queue to the input queue when update of the table to which the update information is added is all completed.
    Type: Application
    Filed: May 16, 2016
    Publication date: January 12, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Yasutaka Kanayama, Motoyuki Tanisho
  • Publication number: 20170005939
    Abstract: A control method performed by a network device includes replenishing a token to a token bucket and updating a timestamp indicating an execution time point of a meter operation when a user packet is received from another device, generating a dummy packet different from the user packet for every certain time period, in response to the dummy packet, replenishing the token to the token bucket, updating the timestamp, and discarding the dummy packet, controlling traffic in accordance with the token within the token bucket.
    Type: Application
    Filed: June 21, 2016
    Publication date: January 5, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Motoyuki Tanisho, Tetsuo Ehara, Norihide Kubota, Shigeru Tsukada, Yuji Tanaka
  • Publication number: 20150356724
    Abstract: An information processing apparatus includes a processor and a memory configured to store therein correspondence information defining an association relationship between position of the connection point of circuits and information of wiring which has one end located at the position of the connection point. The processor is configured to identify a first circuit from a group of multiple images representing an overall circuit, acquire, based on the correspondence information, information of a first position of a connection point of a second circuit at which the identified first circuit is coupled and information of a first wiring which one end is located at the first position, extract, from the second image, a partial image that includes images of the first wiring and the connection point at the first position based on the acquired information of the first position and the first wiring, and output the extracted partial image.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 10, 2015
    Applicant: Fujitsu Limited
    Inventors: SHUICHIRO YAMADA, Motoyuki Tanisho
  • Patent number: 8813002
    Abstract: The embodiment is a non-transitory computer readable storage medium storing a design support program which causes a computer to generate design data for a circuit board in which elements are placed. The program causes the computer to perform: storing, in response to an operation input, operation information in an operation storage section; storing a function of a program executed based on the operation input in a function history storage section; upon detection of an operation of a command causing the computer to execute a predetermined function for generating the design data, acquiring a selected element and storing the selected element in an element information storage section; and detecting an abnormal end of the predetermined function to output the function of the program in the function history storage section, the operation information in the operation information storage section, and the element in the element information storage section to a log file.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Limited
    Inventor: Motoyuki Tanisho
  • Publication number: 20140123088
    Abstract: The embodiment is a non-transitory computer readable storage medium storing a design support program which causes a computer to generate design data for a circuit board in which elements are placed. The program causes the computer to perform: storing, in response to an operation input, operation information in an operation storage section; storing a function of a program executed based on the operation input in a function history storage section; upon detection of an operation of a command causing the computer to execute a predetermined function for generating the design data, acquiring a selected element and storing the selected element in an element information storage section; and detecting an abnormal end of the predetermined function to output the function of the program in the function history storage section, the operation information in the operation information storage section, and the element in the element information storage section to a log file.
    Type: Application
    Filed: August 29, 2013
    Publication date: May 1, 2014
    Applicant: Fujitsu Limited
    Inventor: Motoyuki TANISHO
  • Patent number: 8683415
    Abstract: A disclosed method includes: accepting designation of a condition of grouping plural signal lines to be wired from a user; and switching and carrying out a grouping of the plural signal lines into plural groups based on the designated condition and a disposition pattern of start terminals and end terminals of the plural signal lines. The condition may be designated from a first requirement, a second requirement and a third requirement that includes the first requirement and the second requirement and in which a priority is set to the first requirement or the second requirement.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 25, 2014
    Assignee: Fujitsu Limited
    Inventors: Yoshitaka Nishio, Motoyuki Tanisho
  • Patent number: 8484600
    Abstract: A computer-readable medium storing a design program causing a computer to execute a process is provided. The process includes virtually routing, when routing of a wire to be connected between a first component and a second component at least one of which includes a swapping pin is being designed, the wire to be connected between a first pin of the first component and a first counterpart pin of the second component such that implementation of an actual routed wire connected therebetween is secured regardless of a net allocated to the swapping pin, and swapping one of the virtually routed first pin and the virtually routed first counterpart pin with the swapping pin such that the net allocated to the swapping pin is identical to a net allocated to the other one of the virtually routed first pin and the virtually routed first counterpart pin.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: July 9, 2013
    Assignee: Fujitsu Limited
    Inventors: Yoshitaka Nishio, Eiichi Konno, Kazunori Kumagai, Motoyuki Tanisho, Toshiyasu Sakata
  • Patent number: 8443333
    Abstract: A non-transitory computer-readable recording medium storing a design supporting program causes a computer to perform: acquiring non-complying line lengths of a plurality of wiring paths; drawing for each of the wiring paths a wiring pattern connecting a transmission origin and a transmission destination based on a line length and a wiring route of the wiring path; and controlling the drawing to draw a line for each of the wiring paths, the line being divided into a first line amounting to a non-complying line length acquired at the acquiring and a second line being a wiring pass less the non-complying line length.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: May 14, 2013
    Assignee: Fujitsu Limited
    Inventors: Takahiko Orita, Kazunori Kumagai, Yoshitaka Nishio, Ikuo Ohtsuka, Motoyuki Tanisho
  • Publication number: 20130086546
    Abstract: A disclosed method includes: accepting designation of a condition of grouping plural signal lines to be wired from a user; and switching and carrying out a grouping of the plural signal lines into plural groups based on the designated condition and a disposition pattern of start terminals and end terminals of the plural signal lines. The condition may be designated from a first requirement, a second requirement and a third requirement that includes the first requirement and the second requirement and in which a priority is set to the first requirement or the second requirement.
    Type: Application
    Filed: September 14, 2012
    Publication date: April 4, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Yoshitaka NISHIO, Motoyuki Tanisho
  • Patent number: 8402414
    Abstract: A computer-readable, non-transitory medium stores therein a design support program that causes a computer executing tentative wiring processing between a first terminal group and a second terminal group in a tentative wiring area to execute a process. The process includes detecting unwired nets occurring in the tentative wiring area consequent to the tentative wiring processing; updating the tentative wiring area by expanding the tentative wiring area according to the number of unwired nets, if any unwired nets are detected at the detecting; controlling to execute the tentative wiring processing and the subsequent detecting with respect to the tentative wiring area updated at the updating; and determining the tentative wiring area to be a wiring area if no unwired nets are detected at the detecting.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: March 19, 2013
    Assignee: Fujitsu Limited
    Inventors: Motoyuki Tanisho, Toshiyasu Sakata, Yoshitaka Nishio, Ikuo Ohtsuka, Kazunori Kumagai
  • Publication number: 20120117529
    Abstract: A computer-readable medium storing a design program causing a computer to execute a process is provided. The process includes virtually routing, when routing of a wire to be connected between a first component and a second component at least one of which includes a swapping pin is being designed, the wire to be connected between a first pin of the first component and a first counterpart pin of the second component such that implementation of an actual routed wire connected therebetween is secured regardless of a net allocated to the swapping pin, and swapping one of the virtually routed first pin and the virtually routed first counterpart pin with the swapping pin such that the net allocated to the swapping pin is identical to a net allocated to the other one of the virtually routed first pin and the virtually routed first counterpart pin.
    Type: Application
    Filed: August 30, 2011
    Publication date: May 10, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Yoshitaka Nishio, Eiichi Konno, Kazunori Kumagai, Motoyuki Tanisho, Toshiyasu Sakata
  • Publication number: 20110231810
    Abstract: A computer-readable, non-transitory medium stores therein a design support program that causes a computer executing tentative wiring processing between a first terminal group and a second terminal group in a tentative wiring area to execute a process. The process includes detecting unwired nets occurring in the tentative wiring area consequent to the tentative wiring processing; updating the tentative wiring area by expanding the tentative wiring area according to the number of unwired nets, if any unwired nets are detected at the detecting; controlling to execute the tentative wiring processing and the subsequent detecting with respect to the tentative wiring area updated at the updating; and determining the tentative wiring area to be a wiring area if no unwired nets are detected at the detecting.
    Type: Application
    Filed: February 24, 2011
    Publication date: September 22, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Motoyuki TANISHO, Toshiyasu SAKATA, Yoshitaka NISHIO, Ikuo OHTSUKA, Kazunori KUMAGAI
  • Publication number: 20110225561
    Abstract: A non-transitory computer-readable recording medium storing a design supporting program causes a computer to perform: acquiring non-complying line lengths of a plurality of wiring paths; drawing for each of the wiring paths a wiring pattern connecting a transmission origin and a transmission destination based on a line length and a wiring route of the wiring path; and controlling the drawing to draw a line for each of the wiring paths, the line being divided into a first line amounting to a non-complying line length acquired at the acquiring and a second line being a wiring pass less the non-complying line length.
    Type: Application
    Filed: March 9, 2011
    Publication date: September 15, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Takahiko ORITA, Kazunori KUMAGAI, Yoshitaka NISHIO, Ikuo OHTSUKA, Motoyuki TANISHO
  • Publication number: 20110093829
    Abstract: A non-transitory, computer-readable recording medium stores therein a design support program that causes a computer to execute selecting a wiring path whose line length is greatest among a plurality of wiring paths making up a wiring group leading from a transmission origin to a transmission destination; detecting insufficient line lengths of the wiring paths not selected, insufficiency being determined with respect to the line length of the selected wiring path; calculating the area of insufficiency according to a sum of the detected insufficient line lengths; allocating to a vicinity of the wiring group, a line length adjustment region corresponding to a sum of the areas of insufficiency calculated at calculating; and controlling a display screen to display the wiring group and the allocated line length adjustment region.
    Type: Application
    Filed: October 14, 2010
    Publication date: April 21, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Takahiko Orita, Kazunori Kumagai, Yoshitaka Nishio, Ikuo Ohtsuka, Motoyuki Tanisho