Abstract: The present invention provides a method and apparatus of controlling an operational status of an electronic device which receives data through a HDMI port. The present invention determines whether to wake up the electronic device from the power saving mode according to counting numbers generated based on the transitions of signals within a time period.

Abstract: A data receiver and a method for adjusting the same are provided. The data receiver has an equalizer, a clock data recovery unit, an equalizer controller, and a decoder. The equalizer compensates incoming signal according to a configuration, and outputs corrected signal. The CDR unit uses a clock to sample the corrected signal from the equalizer and generates phase information of the clock. The decoder decodes the raw data. Each cycle of the clock is divided into a plurality of phases, and the phase information indicates the one of the phases that the corrected signal sampled therein. In a testing mode, the equalizer controller applies a plurality of setup values to the configuration individually and records the phase information for tuning the configuration. Therefore, the accuracy of the equalizer is improved and the good signal quality is obtained.

Abstract: The present invention provides a method and apparatus of controlling an operational status of an electronic device which receives data through a HDMI port. The present invention determines whether to wake up the electronic device from the power saving mode according to counting numbers generated based on the transitions of signals within a time period.

Abstract: A clock recovery device includes a PLL circuit and a tuning circuit. The PLL circuit includes a first frequency divider, a second frequency divider, and a clock recovery unit. The first frequency divider divides a first frequency of the input clock by a first divisor to generate a reference signal. The second frequency divider divides a second frequency of the output clock by a second divisor to generate a feedback signal. The clock recovery unit is coupled to the first frequency divider and the second frequency divider, for re-building and providing the output clock according to the reference signal and the feedback signal. The tuning circuit is coupled to the PLL circuit, for tuning at least one of the first divisor and the second divisor of the PLL circuit according to a buffer status information of a data buffer.

Abstract: A method of for accessing a first-in-first-out (FIFO) buffer is provided. The method comprises the following two steps. Firstly, issue a request to access a memory when the amount of the data buffered in the FIFO buffer is more than a threshold. Second, pop the data buffered in the FIFO buffer out to access the memory when the request is granted. If the FIFO buffer is a single-port FIFO buffer, the threshold is set based on the burst length of one burst of data. If the FIFO buffer is a dual-port FIFO buffer, the threshold is set based on the speed at which the data is pushed into the FIFO buffer and the speed at which the data is popped out of the FIFO buffer.

Abstract: A data receiver and a method for adjusting the same are provided. The data receiver has an equalizer, a clock data recovery unit, an equalizer controller, and a decoder. The equalizer compensates incoming signal according to a configuration, and outputs corrected signal. The CDR unit uses a clock to sample the corrected signal from the equalizer and generates phase information of the clock. The decoder decodes the raw data. Each cycle of the clock is divided into a plurality of phases, and the phase information indicates the one of the phases that the corrected signal sampled therein. In a testing mode, the equalizer controller applies a plurality of setup values to the configuration individually and records the phase information for tuning the configuration. Therefore, the accuracy of the equalizer is improved and the good signal quality is obtained.

Abstract: An image processing system is provided comprising a memory, a graphic engine and a data processing module. The graphic engine generates a sequence of input data, wherein each of the input data has an address information pointing to a corresponding memory address of the memory. The data processing module sequentially receives the input data from the graphic engine, buffers each of the received data into a corresponding buffer according to the address information thereof, and outputs buffered data in a buffer to the memory when the buffer is full, wherein memory addresses of the outputted data are continuous.

Abstract: A method of for accessing a first-in-first-out (FIFO) buffer is provided. The method comprises the following two steps. Firstly, issue a request to access a memory when the amount of the data buffered in the FIFO buffer is more than a threshold. Second, pop the data buffered in the FIFO buffer out to access the memory when the request is granted. If the FIFO buffer is a single-port FIFO buffer, the threshold is set based on the burst length of one burst of data. If the FIFO buffer is a dual-port FIFO buffer, the threshold is set based on the speed at which the data is pushed into the FIFO buffer and the speed at which the data is popped out of the FIFO buffer.