Abstract: A semiconductor device and method of forming the same are disclosed. The method includes receiving a substrate having an active fin, an oxide layer over the active fin, a dummy gate stack over the oxide layer, and a spacer feature over the oxide layer and on sidewalls of the dummy gate stack. The method further includes removing the dummy gate stack, resulting in a first trench; etching the oxide layer in the first trench, resulting in a cavity underneath the spacer feature; depositing a dielectric material in the first trench and in the cavity; and etching in the first trench so as to expose the active fin, leaving a first portion of the dielectric material in the cavity.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a first gate structure and a second gate structure formed over the substrate. The semiconductor structure further includes first recesses formed in the substrate adjacent to the first gate structure and first strained source and drain structures formed in the first recesses. The semiconductor structure further includes second recesses formed in the substrate adjacent to the second gate structure and second strained source and drain structures formed in the second recesses. In addition, each of the first recesses has a shape of a trapezoid, and each of the second recesses has a shape of an inverted trapezoid.

Abstract: A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

Abstract: Some embodiments of the present disclosure provide a semiconductor structure, including a substrate having a top surface; a first doped region in proximity to the top surface; a non-doped region positioned in proximity to the top surface and adjacent to the first doped region, having a first width; a metal gate positioned over the non-doped region and over a portion of the first doped region, having a second width. The first width is smaller than the second width, and material constituting the non-doped region is different from material constituting the substrate.

Abstract: The present disclosure provide a semiconductor structure, including a substrate having a top surface; a gate over the substrate, the gate including a footing region in proximity to the top surface, the footing region including a footing length laterally measured at a height under 10 nm above the top surface; and a spacer surrounding a sidewall of the gate, including a spacer width laterally measured at a height of from about 10 nm to about 200 nm above the top surface. The footing length is measured, along the top surface, from an end of a widest portion of the footing region to a vertical line extended from an interface between a gate body and the spacer, and the spacer width is substantially equal to or greater than the footing length.

Abstract: A semiconductor structure includes a semiconductor substrate and a shallow trench isolation (STI). The STI includes a sidewall interfacing with the semiconductor substrate. The STI extrudes from a bottom portion of the semiconductor substrate, and the STI includes a bottom surface contacting the bottom portion of the semiconductor substrate; a top surface opposite to the bottom surface. The bottom surface includes a width greater than a width of the top surface.

Abstract: A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure also includes a dielectric structure over the semiconductor substrate and adjacent to the gate stack. The dielectric structure is in direct contact with the work function layer and the metal filling.

Abstract: A method for detecting abnormal operation of a manufacturing process, comprising the steps of: (a) detecting at least one acoustic signal created from a processing apparatus; (b) transforming the acoustic signal into a frequency spectrum; (c) comparing the frequency spectrum with a pre-determined frequency spectrum, and (d) generating a signal indicating an abnormal operation of the processing apparatus, if an amplitude of at least one first frequency of the frequency spectrum is substantially different from an amplitude of the same frequency of the pre-determined frequency spectrum.

Abstract: An apparatus for fault detection and classification (FDC) specification management including a storage device and a process module. The storage device stores a specification management record and a chart profile record. The specification management record stores statistical algorithm settings of a parameter and the chart profile record stores chart frame and alarm condition information. The process module, which resides in a memory, receives a manipulation message corresponding to the specification management record, and accordingly manipulates the chart profile record.

Abstract: A system and method for automatic SPC chart generation including a storage device and a data acquisition module. The storage device stores a chamber management tree, a recipe window management tree, a parameter configuration table and multiple chart profile records. The data acquisition module, which resides in a memory, acquires multiple process events and parameter values corresponding to the process events and a process parameter, selects a relevant statistical algorithm, calculates a statistical value by applying the statistical algorithm to the parameter values, creates a new chart profile record and a parameter statistics record therein if the chart profile record is absent, and stores the statistical values and measured time in the parameter statistics record.

Abstract: An apparatus for fault detection and classification (FDC) specification management including a storage device and a process module. The storage device stores a specification management record and a chart profile record. The specification management record stores statistical algorithm settings of a parameter and the chart profile record stores chart frame and alarm condition information. The process module, which resides in a memory, receives a manipulation message corresponding to the specification management record, and accordingly manipulates the chart profile record.

Abstract: A system and method for automatic SPC chart generation including a storage device and a data acquisition module. The storage device stores a chamber management tree, a recipe window management tree, a parameter configuration table and multiple chart profile records. The data acquisition module, which resides in a memory, acquires multiple process events and parameter values corresponding to the process events and a process parameter, selects a relevant statistical algorithm, calculates a statistical value by applying the statistical algorithm to the parameter values, creates a new chart profile record and a parameter statistics record therein if the chart profile record is absent, and stores the statistical values and measured time in the parameter statistics record.

Abstract: A temperature-sensing wafer position detection system and method which uses temperature to determine whether a wafer is properly positioned on a bake plate prior to commencement of a photolithography baking process, for example. The system includes a bake plate and a temperature-sensing apparatus which engages the bake plate and measures the change in temperature (?T) of the bake plate over a specified time interval to determine whether the wafer is properly or improperly positioned on the support. In the event that the ?T of the bake plate is at least as great as a given temperature change threshold value over a specified time interval, this indicates that the wafer is properly positioned for processing.

Abstract: A method of building a problem troubleshooting database for use in a semiconductor manufacturing system includes storing semiconductor manufacturing problem data in a problem troubleshooting database; storing cause data in the problem troubleshooting database, the cause data being associated with respective problem data; storing solution data in the problem troubleshooting database, the solution data being associated with respective semiconductor manufacturing problem data and cause data; evaluating the effectiveness of the solution data; and updating the solution data with information with respect to the effectiveness determined in the evaluating step.

Abstract: A temperature-sensing wafer position detection system and method which uses temperature to determine whether a wafer is properly positioned on a bake plate prior to commencement of a photolithography baking process, for example. The system includes a bake plate and a temperature-sensing apparatus which engages the bake plate and measures the change in temperature (?T) of the bake plate over a specified time interval to determine whether the wafer is properly or improperly positioned on the support. In the event that the ?T of the bake plate is at least as great as a given temperature change threshold value over a specified time interval, this indicates that the wafer is properly positioned for processing.

Abstract: An exhaust adaptor and method which includes attachment of an exhaust bellow or conduit to a process chamber to facilitate vacuum-induced evacuation of residual toxic gases from the chamber during cleaning and/or maintenance of the chamber. A throttle valve of the chamber is first removed from a throttle valve housing, and one end of the exhaust adaptor is next attached to the throttle valve housing. An exhaust bellow or conduit is attached to the opposite end of the adaptor. As a down flow of air is directed into the open chamber, vacuum pressure is induced in the chamber interior through the exhaust bellow or conduit, the adaptor and the valve housing, respectively. Air disturbances in the chamber interior are thus eliminated, and toxic residual gases generated in the chamber interior are therefore incapable of diffusing to the exterior of the chamber.

Abstract: The present disclosure provides a smart virtual assistant system to assist in the repair and maintenance of semiconductor tools The virtual assistant system includes an interface for receiving a tool alarm from a specified semiconductor tool and a database including a table for providing information as to what can and cannot be done to the specified semiconductor tool. The virtual assistant system also includes two processing subsystems, one including instructions for deducting tool alarm information from the tool alarm and the other for receiving the tool alarm information, perusing the database, and identifying one or more causes associated with the tool alarm information.

Abstract: A system using backside helium in the processing of wafers in the manufacturing of semiconductor products can cause alarms that can interrupt the manufacturing of the wafers and create damaged wafers. A PID controller responds to the flow of helium gas to generate control signals for operating several algorithms. A filter connected to the output of the PID controller removes unwanted and dangerous noise spikes that have in the past caused a condition called backside alarm. Noise spikes on the dc voltages, the helium supply pressure, the pressure set point, the pressure reading and the non-optimization of the PID controller can cause the alarm.

Abstract: The direct detection of dielectric etch system magnet driver and coil malfunctions is disclosed. A dielectric etch system includes a plasma chamber in which a semiconductor wafer is placed to remove dielectric therefrom, and a number of coils positioned around the chamber to excite the plasma. Magnet drivers of a magnet driver circuitry provide configurable preset current from a power source to the coils. Malfunction detection circuitry includes a number of comparators connected in parallel. Each comparator couples between one of the magnet drivers and one of the coils. A relay couples the comparators to ground, and turns off the power source when any of the comparators yields a substantially non-zero current, which indicates that either the driver or the coil coupled to the comparator is malfunctioning.

Abstract: An exhaust adaptor and method which includes attachment of an exhaust bellow or conduit to a process chamber to facilitate vacuum-induced evacuation of residual toxic gases from the chamber during cleaning and/or maintenance of the chamber. A throttle valve of the chamber is first removed from a throttle valve housing, and one end of the exhaust adaptor is next attached to the throttle valve housing. An exhaust bellow or conduit is attached to the opposite end of the adaptor. As a down flow of air is directed into the open chamber, vacuum pressure is induced in the chamber interior through the exhaust bellow or conduit, the adaptor and the valve housing, respectively. Air disturbances in the chamber interior are thus eliminated, and toxic residual gases generated in the chamber interior are therefore incapable of diffusing to the exterior of the chamber.