Abstract: In one aspect, an apparatus includes a memory repair controller coupled to a memory. The memory repair controller may be configured to provide repair information to cause the memory to disable one or more faulty locations in the memory, and the memory repair controller can be disabled after providing the repair information.

Abstract: An integrated circuit having a secure domain is disclosed. Circuitry within the integrated circuit is used to select one of a plurality of scan modes. The sequence used to select one of the scan modes also serves to reset all of the flip-flops in the secure domain. In this way, it is impossible for a hacker to use the test modes to shift data from the secure domain out of the integrated circuit. The reset is generated asynchronously upon assertion of a first signal and is terminated upon the assertion of a second signal. The assertion of the second signal also serves to select one of the scan modes. This system cannot be hacked by any method that enters scan mode since it is a hardware based solution.

Abstract: In one aspect, an apparatus includes a memory repair controller coupled to a memory. The memory repair controller may be configured to provide repair information to cause the memory to disable one or more faulty locations in the memory, and the memory repair controller can be disabled after providing the repair information.

Abstract: An integrated circuit having a secure domain is disclosed. Circuitry within the integrated circuit is used to select one of a plurality of scan modes. The sequence used to select one of the scan modes also serves to reset all of the flip-flops in the secure domain. In this way, it is impossible for a hacker to use the test modes to shift data from the secure domain out of the integrated circuit. The reset is generated asynchronously upon assertion of a first signal and is terminated upon the assertion of a second signal. The assertion of the second signal also serves to select one of the scan modes. This system cannot be hacked by any method that enters scan mode since it is a hardware based solution.

Abstract: Techniques and solutions are described for providing high-availability computing resources to service client requests. Groups of computing nodes are organized into loops, a given loop being configured to execute a particular subset of tasks, such as tasks with a hash value in a particular ranged serviced by a loop. Computing nodes within a loop can evaluate a task request to determine whether the task request conflicts with another task currently assigned to a node. If a computing node which sent out a task request determines that no conflict was identified, it can execute the task request. Communications within a loop can occur unidirectionally, such that a node which initiated a communication will receive the communication from the last loop node. Loops can be connected to form a ribbon, the ribbon providing a namespace for task execution, where hash ranges for the namespace are uniquely assigned to loops of the ribbon.

Abstract: Embodiments of improved systems and methods are provided herein to reset all datapath logic within a peripheral slave device having multiple clock domains. An embodiment of the disclosed method includes receiving a reset request from a host clock device to reset the peripheral slave device, synchronizing the received reset request to each peripheral clock domain included within the peripheral slave device, and using the synchronized reset request generated within each peripheral clock domain to reset datapath logic contained within that peripheral clock domain.

Abstract: Embodiments of improved systems and methods are provided herein to reset all datapath logic within a peripheral slave device having multiple clock domains. An embodiment of the disclosed method includes receiving a reset request from a host clock device to reset the peripheral slave device, synchronizing the received reset request to each peripheral clock domain included within the peripheral slave device, and using the synchronized reset request generated within each peripheral clock domain to reset datapath logic contained within that peripheral clock domain.

Abstract: In one embodiment, an apparatus includes: a digital-to-analog converter (DAC) circuit having a digital portion to receive a digital value and an analog portion to generate an analog voltage based on the digital value; and a refresh circuit coupled to the DAC circuit to clock gate provision of a first clock signal to the DAC circuit when the digital portion is inactive.

Abstract: In one embodiment, an apparatus includes: a digital-to-analog converter (DAC) circuit having a digital portion to receive a digital value and an analog portion to generate an analog voltage based on the digital value; and a refresh circuit coupled to the DAC circuit to clock gate provision of a first clock signal to the DAC circuit when the digital portion is inactive.

Abstract: Techniques and solutions are described for providing high-availability computing resources to service client requests. Groups of computing nodes are organized into loops, a given loop being configured to execute a particular subset of tasks, such as tasks with a hash value in a particular ranged serviced by a loop. Computing nodes within a loop can evaluate a task request to determine whether the task request conflicts with another task currently assigned to a node. If a computing node which sent out a task request determines that no conflict was identified, it can execute the task request. Communications within a loop can occur unidirectionally, such that a node which initiated a communication will receive the communication from the last loop node. Loops can be connected to form a ribbon, the ribbon providing a namespace for task execution, where hash ranges for the namespace are uniquely assigned to loops of the ribbon.

Abstract: Embodiments are disclosed for systems and methods that include pulsing a clock pin of retention cells included within a scan chain to shift a sequence of logic values into the scan chain, so that successive cells are loaded with opposite logic values. Embodiments also include pulsing a retain pin to retain the logic values, and pulsing the clock pin to shift the sequence of logic values through the chain, so that retained logic values are output from, and logic values opposite to the retained logic values are loaded into, the cells. Embodiments also include pulsing a restore pin to restore the retained logic values, pulsing the clock pin to shift the logic values out of the scan chain, comparing the logic values shifted out of the scan chain with the logic values shifted into the scan chain, and detecting a fault on the retain pin based on said comparison.