Patents by Inventor Muhammad Kazim Hafeez

Muhammad Kazim Hafeez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Techniques for determining timestamp inaccuracies in a transceiver
    Patent number: 11652561
    Abstract: An integrated circuit has a transceiver circuit and a memory circuit. The transceiver circuit includes stage circuits that each perform at least one function specified by a data transmission protocol. The transceiver circuit is coupled to receive packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving each of the packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a trigger indicating receipt of a predefined reference point in each of the packets of timing test patterns. The memory circuit stores each of the timestamps generated by the stage circuits in response to a respective one of the triggers and outputs the timestamps for analysis.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: May 16, 2023
    Assignee: Intel Corporation
    Inventors: Han Hua Leong, Sita Rama Chandrasekhar Mallela, Muhammad Kazim Hafeez, Ming-Shiung Chen, Anuj Agrawal
  • Techniques For Determining Timestamp Inaccuracies In A Transceiver
    Publication number: 20190319729
    Abstract: An integrated circuit has a transceiver circuit and a memory circuit. The transceiver circuit includes stage circuits that each perform at least one function specified by a data transmission protocol. The transceiver circuit is coupled to receive packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving each of the packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a trigger indicating receipt of a predefined reference point in each of the packets of timing test patterns. The memory circuit stores each of the timestamps generated by the stage circuits in response to a respective one of the triggers and outputs the timestamps for analysis.
    Type: Application
    Filed: June 21, 2019
    Publication date: October 17, 2019
    Applicant: Intel Corporation
    Inventors: Han Hua Leong, Sita Rama Chandrasekhar Mallela, Muhammad Kazim Hafeez, Ming-Shiung Chen, Anuj Agrawal