Patents by Inventor Muhammad Yasin

Muhammad Yasin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10990580
    Abstract: An exemplary system, method and computer-accessible medium for modifying a design of an integrated circuit(s) (ICs), which can include, for example, modifying a logic gate(s) in the design for a protected input pattern(s), and providing a restoration unit(s) into the design, where the restoration unit(s) can be configured to (i) produce an error-free output(s) when a correct secret key can be applied to the restoration unit(s), and (ii) produce an erroneous output(s) when an incorrect key can be applied to the restoration unit(s); and ensure that the modified design along with the restoration unit produces at least one erroneous output with respect to the original design for only a pre-determined constant number of incorrect keys based on at least one input pattern.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: April 27, 2021
    Assignees: NEW YORK UNIVERSITY, BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Ozgur Sinanoglu, Jeyavijayan Rajendran, Muhammad Yasin
  • Patent number: 10853523
    Abstract: Exemplary embodiment of the present disclosure can include, for example, a logic-locking circuit (“SARLock”), which can include a logic cone(s) receiving a distinguishing input pattern(s) (DIP), a comparator(s) receiving the DIP(s) and a key value(s), and a logic gate(s) connected to an output of the logic cone and to an output of the comparator. A mask(s) can be connected to the comparator(s) and the logic gate(s). The logic gate(s) can be a XOR gate(s). The comparator(s) can be configured to flip a signal(s) based on a combination of the DIP(s) and the key value(s). A mask(s) can be connected to the comparator(s) and the logic gate(s), which can be configured to prevent the flipped signal(s) from being asserted for a correct key value(s).
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: December 1, 2020
    Assignee: New York University in Abu Dhabi Corporation
    Inventors: Ozgur Sinanoglu, Muhammad Yasin, Jeyavijayan Rajendra
  • Patent number: 10642947
    Abstract: Exemplary embodiments of the present disclosure can include an exemplary system, method and computer-accessible medium for camouflaging a design of an integrated circuit(s) (IC), can include, for example, receiving information related to a plurality of input combinations to the ICs, and camouflaging the design of the ICs by limiting a discriminating ability of the input combination to a predetermined constant number of incorrect assignments. An incorrect output can be intentionally produced for a predetermined constant number of secret minterms of the ICs. An output of the ICs can be restored for the secret minterms using a CamoFix block. The CamoFix block can include a CamoInputMapping block(s), a CamoSecGen block(s) or a comparator block(s).
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: May 5, 2020
    Assignee: New York University
    Inventors: Ozgur Sinanoglu, Jeyavijayan Rajendran, Muhammad Yasin
  • Publication number: 20190340394
    Abstract: Exemplary embodiment of the present disclosure can include, for example, a logic-locking circuit (“SARLock”), which can include a logic cone(s) receiving a distinguishing input pattern(s) (DIP), a comparator(s) receiving the DIP(s) and a key value(s), and a logic gate(s) connected to an output of the logic cone and to an output of the comparator. A mask(s) can be connected to the comparator(s) and the logic gate(s). The logic gate(s) can be a XOR gate(s). The comparator(s) can be configured to flip a signal(s) based on a combination of the DIP(s) and the key value(s). A mask(s) can be connected to the comparator(s) and the logic gate(s), which can be configured to prevent the flipped signal(s) from being asserted for a correct key value(s).
    Type: Application
    Filed: March 20, 2017
    Publication date: November 7, 2019
    Inventors: OZGUR SINANOGLU, MUHAMMAD YASIN, JEYAVIJAYAN RAJENDRAN
  • Publication number: 20190129892
    Abstract: An exemplary system, method and computer-accessible medium for modifying a design of an integrated circuit(s) (ICs), which can include, for example, modifying a logic gate(s) in the design for a protected input pattern(s), and providing a restoration unit(s) into the design, where the restoration unit(s) can be configured to (i) produce an error-free output(s) when a correct secret key can be applied to the restoration unit(s), and (ii) produce an erroneous output(s) when an incorrect key can be applied to the restoration unit(s); and ensure that the modified design along with the restoration unit produces at least one erroneous output with respect to the original design for only a pre-determined constant number of incorrect keys based on at least one input pattern.
    Type: Application
    Filed: October 25, 2018
    Publication date: May 2, 2019
    Inventors: Ozgur Sinanoglu, Jeyavijayan Rajendran, Muhammad Yasin
  • Publication number: 20180232479
    Abstract: Exemplary embodiments of the present disclosure can include an exemplary system, method and computer-accessible medium for camouflaging a design of an integrated circuit(s) (IC), can include, for example, receiving information related to a plurality of input combinations to the ICs, and camouflaging the design of the ICs by limiting a discriminating ability of the input combination to a predetermined constant number of incorrect assignments. An incorrect output can be intentionally produced for a predetermined constant number of secret minterms of the ICs. An output of the ICs can be restored for the secret minterms using a CamoFix block. The CamoFix block can include a CamoInputMapping block(s), a CamoSecGen block(s) or a comparator block(s).
    Type: Application
    Filed: September 6, 2017
    Publication date: August 16, 2018
    Inventors: Ozgur Sinanoglu, Jeyavijayan Rajendran, Muhammad Yasin