Abstract: A converter circuit for converting binary logic signals from a CMOS circuit into binary signals for an ECL circuit. Two output transistors in the converter circuit are connected in parallel between the V.sub.DD CMOS supply voltage and the output of the converter circuit. The resistance across the drain-to-source terminals of the output transistors form a voltage divider network with a pulldown resistor in the ECL circuit. In one embodiment, one of the output transistors is enabled by a logic "1" from the CMOS circuit and the other is enabled only by a logic "0". In another embodiment, one output transistor is always enabled and the other is enabled only by a logic "0" from the CMOS circuit. In both embodiments, the effective resistance across the parallel transistors is different for a logic level "1" and a logic level "0", so that the voltage at the output is also different.

Abstract: A converter circuit for converting signals from a non-CMOS circuit into signals for a CMOS circuit. A level shifter stage in the circuit has a first MOS transistor for receiving at its gate the non-CMOS signals which always enable the first transistor and a second MOS transistor for receiving at its gate a constant voltage for enabling the second transistor. Since these transistors do not switch between non-enabling and enabling conditions in order to change the logic levels at the output of the converter circuit, the circuit operates quickly. In one embodiment the converter circuit converts ECL signals into CMOS signals, and in a second embodiment the converter circuit converts TTL signals into CMOS signals.

Abstract: An ECL to CMOS converter which connects the ECL input signal directly to the source electrode of a MOS gate, and the gate electrode of the MOS gate is independently regulated by connection to a reference voltage that is current sinked through a D.C. path to the negative CMOS voltage supply terminal. The drain electrode of the MOS gate is connected to the input of a CMOS inverter to provide the necessary logic level shift. Another MOS gate provides a D.C. signal path by connecting the input of the CMOS inverter to the negative CMOS voltage supply terminal.

Abstract: The present invention is an Exclusive-OR circuit which uses a minimum number of components and which is particularly adapted for use as a building block for a parity checking circuit. The circuit only uses CMOS gates to reduce the number of included transistors.