Abstract: An ATM multiplexing system comprising a plurality of ATM cell input circuits, each of which stores a cell stream incoming from a corresponding input stage and absorbs and removes instantaneous displacement of the incoming cells, a priority encoder for receiving simultaneously FIFO storage level information from the ATM cell input circuits and determining a priority for processing first an input stage with the largest number of stored cells, the FIFO storage level information including the number of the cells stored in the ATM cell input circuits, a link table processing circuit for receiving output headers from the priority encoder and input port numbers corresponding to the received headers and outputting changed headers corresponding to the received headers, an ATM cell output circuit for receiving the changed headers and link information from the link table processing circuit, determining a cell transmission order according to a service priority and performing a header assembling function for perfect cell

Abstract: A high speed ATM cell synchronizing switching apparatus is disclosed, and the apparatus includes: a plurality of ATM cell inputting circuits 1 for receiving optical ATM signals; a routing control circuit 2 for receiving address information; a cell gate circuit 3 for transmitting the inputted cells synchronously; a switching information tabling circuit 4 for switching the switching information; and a switching matrix circuit 5 for receiving and outputting the switching control information and the cell data information.