Abstract: According to a certain embodiment, the semiconductor integrated circuit includes: first and second power source lines disposed to extend in a first direction; a third power source line disposed in parallel to the first power supply line in a second direction, and having an electric potential equivalent to that of the second power source line; a fourth power source line disposed in parallel to the second power supply line and having an electric potential equivalent to that of the first power source line; a first transistor disposed below the first power supply line and including a first active region; a second transistor disposed below the second power source line and including a second active region; a third transistor disposed between the first active region and the third power source line and including a third active region; and a fourth transistor including a fourth active region.

Abstract: A semiconductor integrated circuit includes a first power line to which a first voltage is continuously applied, a second power line, a power switch cell connected to the first power line and configured to output a second voltage to the second power line according to a first signal, a logic circuit driven by the second voltage applied via the second power line, a first circuit driven by the second voltage applied via the second power line and configured to output a third voltage to logic circuit according to a second signal which is an inverted signal of the first signal, and a second circuit driven by the second voltage applied via the second power line and configured to output a fourth voltage to logic circuit according to a third signal which is an inverted signal of the second signal, the fourth voltage being lower than the third voltage.

Abstract: A semiconductor integrated circuit includes a first power line to which a first voltage is continuously applied, a second power line, a power switch cell connected to the first power line and configured to output a second voltage to the second power line according to a first signal, a logic circuit driven by the second voltage applied via the second power line, a first circuit driven by the second voltage applied via the second power line and configured to output a third voltage to logic circuit according to a second signal which is an inverted signal of the first signal, and a second circuit driven by the second voltage applied via the second power line and configured to output a fourth voltage to logic circuit according to a third signal which is an inverted signal of the second signal, the fourth voltage being lower than the third voltage.

Abstract: A semiconductor integrated circuit comprises first and second transistors, and a resistive element. The first transistor includes first and second regions of first conductivity type in a first well region of opposite conductivity type, and a first gate electrode on the first well region between the first and second regions. The second transistor includes third and fourth region of second conductivity type in a second well region of opposite conductivity type, and a second gate electrode on the second well region between the third and fourth regions. The first region is connected to a first line, and the third and fourth regions are connected to a second line. The resistance element includes a first end connected to the first and second gate electrodes, a second end connected to the second line, and a resistive electrical path between the first and second ends including a portion of the third region.

Abstract: According to one embodiment, a semiconductor integrated circuit comprises: a first flip-flop including a first input circuit, a first latch, a second latch, and a first output circuit; a second flip-flop including a second input circuit, a third latch, a fourth latch, and a second output circuit; and a clock buffer configured to output a common clock signal to the first flip-flop and the second flip-flop. A first output terminal of the second latch is coupled to an input terminal of the first output circuit, and a second output terminal of the second latch is directly coupled to an input terminal of the second input circuit.

Abstract: According to one embodiment, a semiconductor integrated circuit comprises: a first flip-flop including a first input circuit, a first latch, a second latch, and a first output circuit; a second flip-flop including a second input circuit, a third latch, a fourth latch, and a second output circuit; and a clock buffer configured to output a common clock signal to the first flip-flop and the second flip-flop. A first output terminal of the second latch is coupled to an input terminal of the first output circuit, and a second output terminal of the second latch is directly coupled to an input terminal of the second input circuit.

Abstract: According to one embodiment, a semiconductor integrated circuit comprises: a first flip-flop including a first input circuit, a first latch, a second latch, and a first output circuit; a second flip-flop including a second input circuit, a third latch, a fourth latch, and a second output circuit; and a clock buffer configured to output a common clock signal to the first flip-flop and the second flip-flop. A first output terminal of the second latch is coupled to an input terminal of the first output circuit, and a second output terminal of the second latch is directly coupled to an input terminal of the second input circuit.

Abstract: A semiconductor integrated circuit comprises first and second transistors, and a resistive element. The first transistor includes first and second regions of first conductivity type in a first well region of opposite conductivity type, and a first gate electrode on the first well region between the first and second regions. The second transistor includes third and fourth region of second conductivity type in a second well region of opposite conductivity type, and a second gate electrode on the second well region between the third and fourth regions. The first region is connected to a first line, and the third and fourth regions are connected to a second line. The resistance element includes a first end connected to the first and second gate electrodes, a second end connected to the second line, and a resistive electrical path between the first and second ends including a portion of the third region.

Abstract: According to one embodiment, a semiconductor integrated circuit comprises: a first flip-flop including a first input circuit, a first latch, a second latch, and a first output circuit; a second flip-flop including a second input circuit, a third latch, a fourth latch, and a second output circuit; and a clock buffer configured to output a common clock signal to the first flip-flop and the second flip-flop. A first output terminal of the second latch is coupled to an input terminal of the first output circuit, and a second output terminal of the second latch is directly coupled to an input terminal of the second input circuit.

Abstract: A flip-flop circuit includes a first clocked inverter that is connected to the data terminal at an input node thereof, and outputs a first signal, which is an inversion of the data signal, in accordance with the third and fourth clock signals. The flip-flop circuit includes a first latching inverter that outputs a second signal, which is an inversion of the first signal, at an output node thereof. The flip-flop circuit includes a transfer gate that passes the second signal therethrough and outputs a third signal at an output node thereof in accordance with the first and second clock signals. The flip-flop circuit includes a second latching inverter that is connected to the output node of the transfer gate at an input node thereof and outputs a fourth signal, which is an inversion of the third signal, at an output node thereof.

Abstract: A flip-flop circuit has a master latch circuit and a slave latch circuit. In the flip-flop circuit, the master latch circuit and the slave latch circuit share at least a pair of transistors. In response to the clock signal, the signal held in the master latch circuit can be output at higher speed as the output signal via the intermediate node, the slave latch circuit and the output circuit. The flip-flop circuit can be reduced in cell size and improved in processing speed.

Abstract: A flip-flop circuit has a master latch circuit and a slave latch circuit. In the flip-flop circuit, the master latch circuit and the slave latch circuit share at least a pair of transistors. In response to the clock signal, the signal held in the master latch circuit can be output at higher speed as the output signal via the intermediate node, the slave latch circuit and the output circuit. The flip-flop circuit can be reduced in cell size and improved in processing speed.

Abstract: A semiconductor device includes a flip-flop circuit formed in a CMOS semiconductor integrated circuit. The flip-flop circuit includes at least a first clock generating inverter that generates a first clock signal and a second clock generating inverter that generates a second clock signal obtained by inverting the first clock signal, the first clock generating inverter and the second clock generating inverter are arranged so as to sandwich a latch unit, the latch unit including a master latch unit and a slave latch unit in the flip-flop circuit, the first clock generating inverter and a first other circuit in the flip-flop circuit are configured to share a source region, the first other circuit being adjacent to the first clock generating inverter, and the second clock generating inverter and a second other circuit in the flip-flop circuit are configured to share a source region, the second other circuit being adjacent to the second clock generating inverter.

Abstract: A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.

Abstract: A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.

Abstract: A semiconductor device includes a flip-flop circuit formed in a CMOS semiconductor integrated circuit. The flip-flop circuit includes at least a first clock generating inverter that generates a first clock signal and a second clock generating inverter that generates a second clock signal obtained by inverting the first clock signal, the first clock generating inverter and the second clock generating inverter are arranged so as to sandwich a latch unit, the latch unit including a master latch unit and a slave latch unit in the flip-flop circuit, the first clock generating inverter and a first other circuit in the flip-flop circuit are configured to share a source region, the first other circuit being adjacent to the first clock generating inverter, and the second clock generating inverter and a second other circuit in the flip-flop circuit are configured to share a source region, the second other circuit being adjacent to the second clock generating inverter.

Abstract: A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-contact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.

Abstract: A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.

Abstract: A semiconductor integrated circuit device contains a CMOS circuit that includes a plurality of N-channel transistors and a plurality of P-channel transistors. The plurality of N-channel transistors is provided with device isolation by one of a gate isolation structure and a shallow trench isolation structure. The plurality of P-channel transistors are provided with device isolation by the other of the gate isolation structure and the shallow trench isolation structure.

Abstract: A basic cell placed in a semiconductor device comprises a via contact placed on a wiring grid having a pitch narrower than a pitch between a contact placed in a source region and a contact placed in a drain region of a transistor in a basic cell, and a wiring layer connected to the via contact, being used as a source terminal, a drain terminal, and a gate terminal of the transistor.