Abstract: The stacked semiconductor memory device of the present invention has the object of reducing the cost of developing a wide variety of memory devices and includes: a memory cell array chip that is equipped with memory cell arrays, an interface chip that is stacked with the memory cell array chip and that is provided with a memory configuration switching circuit for changing the input/output bit configuration of the memory cell arrays, and a plurality of interchip wires for connecting the memory cell array chip and the interface chip.

Abstract: In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal transmission between these semiconductor circuit chips, when transmitting signals, only one interchip interconnection that serves for signal transmission is selected and other interchip interconnections are electrically isolated by means of switches that are provided between the interchip interconnections and signal lines. Interchip interconnection capacitance relating to the charge and discharge of interconnections is thus minimized.

Abstract: A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.

Abstract: In a phase locked loop circuit, a phase difference signal (an up signal and a down signal) is supplied from a phase comparator to a serial-to-parallel converting circuit, and an output of the serial-to-parallel converting circuit is supplied to an up-down counter having a count value is counted up or down in accordance with the phase difference detected by the phase comparator. A voltage controlled oscillator generates an oscillation signal having the frequency controlled in accordance with the count value of the up-down counter. Thus, since the phase difference signal is serial-to-parallel converted, the rate of the phase difference signal is lowered, so that the operation speed of the up-down counter can be relaxed. Therefore, the operation speed of the phase locked loop circuit can be elevated with elevating the operation speed of the up-down counter.

Abstract: In a phase comparator, a first data fetching circuit fetches an input signal in response to a transition timing of a clock signal having a frequency about half that of the input signal, and a second data fetching circuit fetches the output signal of the first data fetching circuit in response to a transition timing of an inverted signal of the clock signal. A first exclusive OR performs an exclusive OR operation upon the input signal and the output signal of the first data fetching circuit. and a second exclusive OR circuit performs an exclusive OR operation upon the output signals of the first and second data fetching circuits. An inverter inverts the output signal of the first exclusive OR circuit.

Abstract: In a voltage controlled oscillator including an odd number of inverter circuits connected in a ring shape, at least one of the inverter circuits is constructed by an inverter and a current control circuit connected in series between a pre-stage inverter circuit and post-stage inverter circuit, and a voltage control circuit connected between the pre-stage inverter circuit and the post-stage inverter circuit. The inverter receives an output signal of the pre-stage inverter circuit to generate an inverted signal. The current control circuit supplies a current in accordance with the inverted signal to the post-stage inverter circuit. The current is controlled by an input voltage. The voltage control circuit charges and discharges an input capacitance of the post-stage inverter circuit in accordance with the output signal of the pre-stage inverter circuit.

Abstract: A metal-semiconductor type field effect transistor has a Y-letter shaped gate electrode standing on an active layer, and the Y-letter shaped gate electrode prevents piezoelectric charges induced beneath both ends of the wing portions thereof from undesirable merger so as to restrict variation of the threshold regardless of the orientation of the Y-letter shaped gate electrode.

Abstract: The main surface of a semiconductor substrate, on which a field effect transistor is formed, coincides with the (nm0) lattice plane of the substrate and drain electrode thereof is oriented to flow drain current in a direction parallel to the [mn0] or [mn0] axis, wherein n and m independently represent an arbitrary integer, provided that n and m are not 0 at the same time, and that the quotient n/m (m is not zero) is not an integer. Accordingly, the plane orientation of the substrate and the direction of the drain current have a relationship such that no piezoelectric charges are induced in the channel region of the field effect transistor. Therefore, substantially no piezoelectric charges are generated even when a stress is produced in the dielectric layer formed on the substrate. Moreover, deterioration and variation in the electric characteristics due to the variation in the thickness of the dielectric layer are minimized.