Patents by Inventor Munnangi SIRISHA

Munnangi SIRISHA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11933841
    Abstract: The present disclosure provides a DFT architecture for ICs and a method for testing the ICs with the proposed DFT architecture. The present disclosure also includes a focus on USB PD protocol with respect to the DFT architecture. The present disclosure also includes focus on testing IC with single I/O pin. The DFT architecture primarily comprises of a test mode controller and reuses the USBPD protocol framework logic comprising analog USBPD CC circuitry in analog block and the USBPD signaling, protocol logic in digital block for the test purposes. The DFT architecture is implemented with analog test modes and digital test modes using a single I/O pin, wherein analog test modes comprises of analog trims and observation modes and digital test modes comprises of LBIST, ATPG and digital observation modes. The method disclosed is directed to the functions associated with testing the USBPD ICS using single I/O pin.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: March 19, 2024
    Assignee: SILICONCH SYSTEMS PVT LTD
    Inventors: Munnangi Sirisha, Rakesh Kumar Polasa, Satish Anand Verkila
  • Patent number: 11768529
    Abstract: The present disclosure relates to a system and method for enabling power sharing in a multi-port power sourcing device. The system comprises of a multiport power sourcing device having a plurality of ports and a plurality of pre-defined resistances configured to each port of the plurality of ports and is configured to receive input parameters related to plurality of ports, total power capacity of the device and maximum power of each port, determine a second set of parameters associated with pre-defined resistances, execute a first set of instructions based on the input parameters and the second set of parameters, execute a second set of instructions based on the executed first set of instructions to facilitate implementation via a request-response communication interface to discover and track any or a combination of number and status of the plurality of ports based on the determined second set of parameters.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: September 26, 2023
    Assignee: SILICONCH SYSTEMS PVT LTD
    Inventors: Siva Naga Subrahmanya Saratchandra Bhagavathula, Rakesh Kumar Polasa, Kaustubh Kumar, Munnangi Sirisha
  • Patent number: 11604501
    Abstract: The present disclosure relates to a method and system to facilitate temperature-aware redistribution of power in a power sourcing device comprising plurality of ports. The method can include monitoring, by using one or more sensors coupled to the power sourcing device, a first temperature associated with a first port of the plurality of ports to obtain a first set of signals and executing, at the power sourcing device, based on a second set of signals obtained from the first set of signals, a first set of instructions associated with redistribution of power from the first port to second port of the plurality of ports, wherein the second set of signals can indicate exceeding of the first temperature above the predefined threshold temperature value.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 14, 2023
    Assignee: Siliconch Systems Pvt Ltd
    Inventors: Siva Naga Subrahmanya Saratchandra Bhagavathula, Munnangi Sirisha, Kaustubh Kumar, Rakesh Kumar Polasa
  • Publication number: 20220244309
    Abstract: The present disclosure provides a DFT architecture for ICs and a method for testing the ICs with the proposed DFT architecture. The present disclosure also includes a focus on USB PD protocol with respect to the DFT architecture. The present disclosure also includes focus on testing IC with single I/O pin. The DFT architecture primarily comprises of a test mode controller and reuses the USBPD protocol framework logic comprising analog USBPD CC circuitry in analog block and the USBPD signaling, protocol logic in digital block for the test purposes. The DFT architecture is implemented with analog test modes and digital test modes using a single I/O pin, wherein analog test modes comprises of analog trims and observation modes and digital test modes comprises of LBIST, ATPG and digital observation modes. The method disclosed is directed to the functions associated with testing the USBPD ICS using single I/O pin.
    Type: Application
    Filed: October 6, 2021
    Publication date: August 4, 2022
    Inventors: Munnangi SIRISHA, Rakesh Kumar POLASA, Satish Anand VERKILA
  • Publication number: 20220221921
    Abstract: The present disclosure relates to a system and method for enabling power sharing in a multi-port power sourcing device. The system comprises of a multiport power sourcing device having a plurality of ports and a plurality of pre-defined resistances configured to each port of the plurality of ports and is configured to receive input parameters related to plurality of ports, total power capacity of the device and maximum power of each port, determine a second set of parameters associated with pre-defined resistances, execute a first set of instructions based on the input parameters and the second set of parameters, execute a second set of instructions based on the executed first set of instructions to facilitate implementation via a request-response communication interface to discover and track any or a combination of number and status of the plurality of ports based on the determined second set of parameters.
    Type: Application
    Filed: December 23, 2021
    Publication date: July 14, 2022
    Inventors: Siva Naga Subrahmanya Saratchandra BHAGAVATHULA, Rakesh Kumar POLASA, Kaustubh KUMAR, Munnangi SIRISHA
  • Publication number: 20220171443
    Abstract: The present disclosure relates to a method for facilitating dynamic power allocation and distribution in a multi-port power sourcing device. The method comprises receiving, by a first set of instructions to be executed on a multi-port power sourcing device, the one or more input parameters at the multi-port power sourcing device. The first set of instructions is executed at the multi-port power sourcing device. The first set of instructions pertains to power distribution and operational decision-making across each of the port of the multi-port power sourcing device. Further, a second set of instructions are executed based on the executed first set of instructions. The second set of instructions is executed to manage operations pertaining to a single port of the plurality of ports of the multi-port power sourcing device. The executed first set of instructions control the second set of instructions via a request-response communication interface.
    Type: Application
    Filed: August 31, 2021
    Publication date: June 2, 2022
    Inventors: Kaustubh KUMAR, Rakesh Kumar POLASA, Munnangi SIRISHA, Siva Naga Subrahmanya Saratchandra BHAGAVATHULA
  • Publication number: 20220113776
    Abstract: The present disclosure relates to a method and system to facilitate temperature-aware redistribution of power in a power sourcing device comprising plurality of ports. The method can include monitoring, by using one or more sensors coupled to the power sourcing device, a first temperature associated with a first port of the plurality of ports to obtain a first set of signals and executing, at the power sourcing device, based on a second set of signals obtained from the first set of signals, a first set of instructions associated with redistribution of power from the first port to second port of the plurality of ports, wherein the second set of signals can indicate exceeding of the first temperature above the predefined threshold temperature value.
    Type: Application
    Filed: June 3, 2021
    Publication date: April 14, 2022
    Inventors: Siva Naga Subrahmanya Saratchandra BHAGAVATHULA, Munnangi SIRISHA, Kaustubh KUMAR, Rakesh Kumar POLASA