Patents by Inventor Muriel Martinez

Muriel Martinez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240109875
    Abstract: A novel method for synthesizing NCA compounds. Also, a new use of a peptide coupling agent. The method makes it possible to obtain NCA compounds from ?-amino-acids, under mild and non-racemic reaction conditions, and in the absence of constraining reagents of use, such as phosgene, which may lead to the formation of undesirable by-products.
    Type: Application
    Filed: December 21, 2021
    Publication date: April 4, 2024
    Applicants: ECOLE NATIONALE SUPERIEURE DE CHIMIE DE MONTPELLIER (ENSCM), UNIVERSITE DE MONTPELLIER (UM), CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Guillaume LACONDE, Jean MARTINEZ, Muriel AMBLARD-CAUSSIL
  • Patent number: 8304345
    Abstract: The invention relates to improvements in the polishing of a layer of germanium by a method which includes a first step of chemical-mechanical polishing of the surface of the germanium layer that is carried out with a first polishing solution having an acidic pH. The first polishing step is then followed by a second step of chemical-mechanical polishing of the surface of the germanium layer carried out with a second polishing solution having an alkaline pH. The polished heteroepitaxial germanium layer has a surface microroughness of less than 0.1 nm RMS and a surface macroroughness corresponding to a surface haze level of less than 0.5 ppm.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: November 6, 2012
    Assignee: Soitec
    Inventors: Muriel Martinez, Pierre Bey
  • Publication number: 20110117740
    Abstract: A polishing method for a heterostructure of at least one relaxed superficial heteroepitaxial layer on a substrate made of a different material. The method includes a first chemical mechanical polishing step of the surface of the heteroepitaxial layer performed with a polishing cloth having a first compressibility ratio and with a polishing solution having a first silica particle concentration. The first chemical mechanical polishing step is followed by a second chemical mechanical polishing step of the surface of the heteroepitaxial layer, with the second step being performed with a polishing cloth having a second compressibility ratio, higher than the first compressibility ratio, and with a polishing solution having a second silica particle concentration, lower than the first concentration. By this method, improved surface roughness is achieved.
    Type: Application
    Filed: January 23, 2008
    Publication date: May 19, 2011
    Inventors: Muriel Martinez, Corinue Seguin, Morgane Logiou
  • Publication number: 20110045654
    Abstract: In order to polish a layer of germanium (121), a first step of chemical-mechanical polishing of the surface (121a) of the germanium layer (121) is carried out with a first polishing solution having an acidic pH. The first polishing step is followed by a second step of chemical-mechanical polishing of the surface of the germanium layer (121) carried out with a second polishing solution having an alkaline pH.
    Type: Application
    Filed: June 9, 2009
    Publication date: February 24, 2011
    Inventors: Muriel Martinez, Pierre Bey
  • Patent number: 7718534
    Abstract: A method of planarization of a surface of a heteroepitaxial layer by chemical-mechanical polishing the disturbed surface of the heteroepitaxial layer with a polishing pad having a compressibility greater than 2% and less than 15% and a slurry comprising at least 20% of silica particles having an average diameter between about 70 and about 100 nm. This method allows to reach high polishing rates appropriated for eliminating surface defects on heteroepitaxial layers, such as crosshatch patterns, and to achieve, in the same time, a final polish that is desirable to facilitate further operations.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: May 18, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Muriel Martinez, Frédéric Metral, Patrick Reynaud, Zohra Chahra
  • Patent number: 7406994
    Abstract: An automatic high-precision layer cutting device for separating a layer from a semiconductor substrate. The device includes a fixed positioning member for receiving at least a portion of a semiconductor substrate that has a weakened area therein and a peripheral annular notch located below the weakened area. The positioning member maintains the position of the substrate on a moveable support. A cutting mechanism having at least one blade is provided for contacting the substrate and inducing a cleaving wave therein. The cutting mechanism is operatively associated with the positioning member so that the as at least one blade contacts the annular notch, the positioning member prevents movement of the substrate and the moveable support moves away from the substrate to allow the cleaving wave to both divide the substrate at the notch into first and second parts and detach the layer from the substrate along the weakened area.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: August 5, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Muriel Martinez, Thierry Barge, Alain Soubie, Chrystelle Lagahe-Blanchard, Cécile Berne, Olivier Rayssac
  • Patent number: 7391094
    Abstract: A semiconductor structure includes a substrate having a surface and being made of a material that provides atypical surface properties to the surface, a bonding layer on the surface of the substrate, and a further layer molecularly bonded to the bonding layer. A method for fabricating such a semiconductor structure includes providing a substrate having a surface and being made of a material that provides atypical surface properties to the surface, providing a bonding layer on the surface of the substrate, smoothing the bonding layer to provide a surface that is capable of molecular bonding, and molecularly bonding a further layer to the bonding layer to form the structure. The atypical surface properties preferably include at least one of a roughness of more than 0.5 nm rms, or a roughness of at least 0.4 nm rms that is difficult to polish, or a chemical composition that is incompatible with molecular bonding.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: June 24, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Olivier Rayssac, Muriel Martinez, Sephorah Bisson, Lionel Portigliatti
  • Publication number: 20070122926
    Abstract: An automatic high-precision layer cutting device for separating a layer from a semiconductor substrate. The device includes a fixed positioning member for receiving at least a portion of a semiconductor substrate that has a weakened area therein and a peripheral annular notch located below the weakened area. The positioning member maintains the position of the substrate on a moveable support. A cutting mechanism having at least one blade is provided for contacting the substrate and inducing a cleaving wave therein. The cutting mechanism is operatively associated with the positioning member so that the as at least one blade contacts the annular notch, the positioning member prevents movement of the substrate and the moveable support moves away from the substrate to allow the cleaving wave to both divide the substrate at the notch into first and second parts and detach the layer from the substrate along the weakened area.
    Type: Application
    Filed: January 30, 2007
    Publication date: May 31, 2007
    Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Muriel Martinez, Thierry Barge, Alain Soubie, Chrystelle Lagahe-Blanchard, Cecile Berne, Olivier Rayssac
  • Publication number: 20070087570
    Abstract: A method of planarization of a surface of a heteroepitaxial layer by chemical-mechanical polishing the disturbed surface of the heteroepitaxial layer with a polishing pad having a compressibility greater than 2% and less than 15% and a slurry comprising at least 20% of silica particles having an average diameter between about 70 and about 100 nm. This method allows to reach high polishing rates appropriated for eliminating surface defects on heteroepitaxial layers, such as crosshatch patterns, and to achieve, in the same time, a final polish that is desirable to facilitate further operations.
    Type: Application
    Filed: December 7, 2006
    Publication date: April 19, 2007
    Inventors: Muriel Martinez, Frederic Metral, Patrick Reynaud, Zohra Chahra
  • Patent number: 7189304
    Abstract: An automatic high-precision layer cutting device for separating a layer from a semiconductor substrate. The cutting device includes a fixed positioning member for receiving at least a portion of a semiconductor substrate that has a weakened area therein and a peripheral annular notch that is located below the weakened area. The positioning member maintains a predetermined position of the substrate on a support. The device also includes cutting means having at least one blade for contacting the substrate and for inducing a cleaving wave into the substrate. The cutting means is operatively associated with the positioning member so that the at least one blade contacts the annular notch and the positioning member prevents movement of the substrate. The at least one blade induces a cleaving wave of sufficient intensity to both divide the substrate at the notch into first and second parts and detach the layer from the substrate along the weakened area.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: March 13, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Muriel Martinez, Thierry Barge, Alain Soubie, Chrystelle Lagahe-Blanchard, Cécile Berne, Olivier Rayssac
  • Publication number: 20060086949
    Abstract: A semiconductor structure includes a substrate having a surface and being made of a material that provides atypical surface properties to the surface, a bonding layer on the surface of the substrate, and a further layer molecularly bonded to the bonding layer. A method for fabricating such a semiconductor structure includes providing a substrate having a surface and being made of a material that provides atypical surface properties to the surface, providing a bonding layer on the surface of the substrate, smoothing the bonding layer to provide a surface that is capable of molecular bonding, and molecularly bonding a further layer to the bonding layer to form the structure. The atypical surface properties preferably include at least one of a roughness of more than 0.5 nm rms, or a roughness of at least 0.4 nm rms that is difficult to polish, or a chemical composition that is incompatible with molecular bonding.
    Type: Application
    Filed: December 13, 2005
    Publication date: April 27, 2006
    Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A., a French company
    Inventors: Olivier Rayssac, Muriel Martinez, Sephorah Bisson, Lionel Portigliatti
  • Patent number: 6989314
    Abstract: A semiconductor structure includes a substrate having a surface and being made of a material that provides a typical surface properties to the surface, a bonding layer on the surface of the substrate, and a further layer molecularly bonded to the bonding layer. A method for fabricating such a semiconductor structure includes providing a substrate having a surface and being made of a material that provides a typical surface properties to the surface, providing a bonding layer on the surface of the substrate, smoothing the bonding layer to provide a surface that is capable of molecular bonding, and molecularly bonding a further layer to the bonding layer to form the structure. The a typical surface properties preferably include at least one of a roughness of more than 0.5 nm rms, or a roughness of at least 0.4 nm rms that is difficult to polish, or a chemical composition that is incompatible with molecular bonding.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: January 24, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Olivier Rayssac, Muriel Martinez, Sephorah Bisson, Lionel Portigliatti
  • Patent number: 6858517
    Abstract: The present invention relates to a method for forming a heterogeneous assembly of first and second materials having different coefficients of thermal expansion. The method includes bonding a surface of a first substrate of a first material to a surface of a second substrate of a second material wherein the first substrate includes a zone of weakness therein to define a transfer layer adjacent the first surface, providing a stiffening substrate of a third material to maintain sufficient flatness and prevent breakage of the transfer layer during detachment from the first substrate, and detaching the transfer layer from the first substrate along the zone of weakness to form a heterogeneous assembly of the transfer layer and second substrate.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: February 22, 2005
    Assignee: S.O.I. Tec Silicon on Insulator Technologies S.A.
    Inventors: Muriel Martinez, Alice Boussagol
  • Publication number: 20040253795
    Abstract: The present invention relates to a method for forming a heterogeneous assembly of first and second materials having different coefficients of thermal expansion. The method includes bonding a surface of a first substrate of a first material to a surface of a second substrate of a second material wherein the first substrate includes a zone of weakness therein to define a transfer layer adjacent the first surface, providing a stiffening substrate of a third material to maintain sufficient flatness and prevent breakage of the transfer layer during detachment from the first substrate, and detaching the transfer layer from the first substrate along the zone of weakness to form a heterogeneous assembly of the transfer layer and second substrate.
    Type: Application
    Filed: May 6, 2004
    Publication date: December 16, 2004
    Inventors: Muriel Martinez, Alice Boussagol
  • Publication number: 20040144487
    Abstract: An automatic high-precision layer cutting device for separating a layer from a semiconductor substrate. The cutting device includes a fixed positioning member for receiving at least a portion of a semiconductor substrate that has a weakened area therein and a peripheral annular notch that is located below the weakened area. The positioning member maintains a predetermined position of the substrate on a support. The device also includes cutting means having at least one blade for contacting the substrate and for inducing a cleaving wave into the substrate. The cutting means is operatively associated with the positioning member so that the at least one blade contacts the annular notch and the positioning member prevents movement of the substrate. The at least one blade induces a cleaving wave of sufficient intensity to both divide the substrate at the notch into first and second parts and detach the layer from the substrate along the weakened area.
    Type: Application
    Filed: October 7, 2003
    Publication date: July 29, 2004
    Inventors: Muriel Martinez, Thierry Barge, Alain Soubie, Chrystelle Lagahe-Blanchard, Cecile Berne, Olivier Rayssac