Abstract: Embodiments include systems and methods for processing Reliability, Availability and Serviceability (RAS) events in a computer system. Embodiments comprise processing critical events in a first portion of a Management Interrupt (MI) period. The MI period is chosen to be not greater than a maximum tolerable Operating System (OS) latency period. If time remains in a current MI period after processing critical events, the system then processes non-critical events during the time remaining in the current MI period. If at the end of the current MI period, some non-critical events remain to be processed, a subsequent MI period is scheduled to process the remaining non-critical events.

Abstract: Machine-readable medium, processes and systems for adding and/or removing components from a running computing device based upon a static topology table and a dynamic topology table are disclosed.

Abstract: Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.

Abstract: Various embodiments described herein include one or more of systems, methods, firmware, and software to synchronize system information between processors during system boot in a links-based multi-processor system. Some embodiments synchronize data block by block through memory rather than piece by piece through registers by allowing a System Bootstrap Processor (“SBSP”) to directly access synchronization data in local memory of each of one or more Application Processors. These and other embodiments are described in greater detail below.

Abstract: In some embodiments a boot progress of a System Boot Strap Processor in a multi-processor system is monitored and a boot processor failure is detected using an Application Processor. If the boot processor failure is detected at least a portion of the system is reinitialized (and/or the system is rebooted). Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for dynamically discovering a topology of a system having a plurality of point-to-point (PTP) links via a routine that communicates a link exchanged parameter with at least one component coupled to a system bootstrap processor (SBSP), sets a minimal set of routing infrastructure information based on the communication, and determines presence of a neighboring component to a target component based on a communication from the SBSP to the target component using the minimal set of routing infrastructure information. Other embodiments are described and claimed.

Abstract: Methods and apparatus to change a configuration of a processor system are disclosed. An example disclosed method calculates system configuration data during a non-quiesce state of a processing system, stores information based on the calculated system configuration data in a data buffer during the non-quiesce state of the processing system, and extracts information from the data buffer to update the configuration of the processing system while the processing system is in a quiesce state.

Abstract: Embodiments include systems and methods for processing Reliability, Availability and Serviceability (RAS) events in a computer system. Embodiments comprise processing critical events in a first portion of a Management Interrupt (MI) period. The MI period is chosen to be not greater than a maximum tolerable Operating System (OS) latency period. If time remains in a current MI period after processing critical events, the system then processes non-critical events during the time remaining in the current MI period. If at the end of the current MI period, some non-critical events remain to be processed, a subsequent MI period is scheduled to process the remaining non-critical events.

Abstract: Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.

Abstract: In some embodiments a boot progress of a System Boot Strap Processor in a multi-processor system is monitored and a boot processor failure is detected using an Application Processor. If the boot processor failure is detected at least a portion of the system is reinitialized (and/or the system is rebooted). Other embodiments are described and claimed.

Abstract: A method is described in which, in response to notice of a configuration event yet to happen within a network that is part of a link-based computing system, a component within said link based computing system: a) identifies networking configuration information changes to be made by components within the link-based computing system; and, b) sends instances of program code to each one of the components. Each instance of program code is to be executed by a specific component that it was sent to. Each instance of program code is customized to implement the particular one or more networking configuration information changes to be made at the specific component it was sent to.

Abstract: Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.