Abstract: A computer system incorporating a memory controller which is capable of working with a write-back cache which operates using burst operations and with ISA and EISA bus masters. A state machine is provided for use with the cache controller and a state machine is provided for use with the EISA and ISA bus masters. When a bus master has requested data which is present only in the cache controller and a write-back operation must be performed, the memory controller halts the operation of the EISA and ISA bus masters until the data can be fully written back by the cache controller. In the case of an EISA bus master, this halting operation is performed by stretching the clocking signal which forms the synchronizing signal for the EISA bus. In the case of ISA bus masters, this halting is done by providing a wait state indication to the ISA bus masters. The state machine responsible for the memory controller cooperating with the bus masters is paused and the state machine for the cache controller is activated.

Abstract: At least two double buffers or FIFOs, each FIFO including a first group of latches in series with a second group of latches, coupled between a host data bus and a corresponding bank or way of interleaved memory. The inputs of the first group of latches are coupled to the host data bus, and the inputs of the second group of latches are coupled to the outputs of the first group of latches of each double buffer or FIFO. The outputs of the second group of latches are coupled to the memory data bus of the corresponding way of interleaved memory. During a burst write sequence, an address is placed on the host address bus and a series of data doublewords are sequentially placed onto the host data bus, while the DRAMs of main memory are entering into page mode. The first group of latches of each double buffer or FIFO latches in every other data doubleword.

Abstract: A circuit determines when a given operation has been performed and starts a counter. If a second operation, particularly an operation complementary to the first operation, is initiated before the counter reaches a predetermined value the second operation is held or delayed until the time is elapsed, after which time the second operation completes.

Abstract: A method for slowing down a high speed microprocessor with an internal cache to maintain compatibility with applications software written for slower speed microprocessors. The internal cache of the processor is invalidated during the slowdown and the cache address comparison circuitry is directed to evaluate external addresses for a preset interval, preventing the processor from accessing the cache, thereby slowing down the processor. The external address evaluation direction is released when a bus requesting device indicates a bus request during the slowdown, allowing the processor to respond to the bus request promptly to prevent possible latency problems from occurring, but still maintaining the processor in a halted state.

Abstract: A memory expansion board capable of holding up to 16 Mbytes of memory devices, using primarily 1 Mbit chips, in 2 Mbyte module increments, on a single IBM PC/AT compatible size board. The circuit board is so designed that when the memory expansion board is populated by modules and placed in a computer system it does not interfere with any of the other expansion slots within the computer system, all of the expansion slots being normally spaced apart. The memory expansion board also includes a means of protecting the memory expansion board and modules from damage due to misalignment when inserting the board and/or modules. When certain of the modules are inserted rotated 180 degrees the circuit board cannot be properly installed in the system board because of physical interference. Lastly, the memory expansion board includes a means for providing reduced length addressing memory lines to memory devices appearing on opposite sides of a circuit board.