Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving, at a circuit, data via a differential input signal, detecting a rising edge in the data received via the differential input signal, and precharging a common mode voltage (Vcm) node of the differential input signal responsive to detecting the rising edge in the data received via the differential input signal, wherein the Vcm node is a floating node.

Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.

Abstract: A phase detector and retimer circuit that includes a retimer circuit, a phase shift circuit coupled to the retimer circuit, and an error signal generation circuit coupled to the retimer circuit and the phase shift circuit. The retimer circuit is configured to receive a data signal and generate a first retimed data signal based on a first phase of a clock signal and a second retimed data signal based on a second phase of the clock signal. The phase shift circuit is configured to receive the data signal and phase shift the data signal to generate first, second, third, and fourth phase shifted data signals. The error signal generation circuit is configured to generate a first error signal and a second error signal based on the first and second retimed data signals and the first, second, third, and fourth phase shifted data signals.

Abstract: A loss of lock detector that includes a logic gate, a voltage-to-current converter coupled to the logic gate, a capacitor coupled to the converter, and a comparator coupled to the capacitor. The logic gate is configured to receive a first error signal and a second error signal from a phase detector, perform an AND function of the first and second error signals, and generate a gate output signal. The converter is configured to receive the gate output signal and generate a stream of current pulses representative of the gate output signal. The capacitor is configured to receive the stream of current pulses and generate a DC signal representative of the stream of current pulses. The comparator is configured to compare the DC signal to a reference signal and output a lock signal.

Abstract: A current mode logic (CML) latch that includes a first transistor coupled to a second transistor, a third transistor coupled to a fourth transistor, a first capacitor connected to the first, second, third, and fourth transistors, and a second capacitor cross-coupled with the first capacitor and connected to the third and fourth transistors. The first and second transistors are configured to receive a data signal. The third and fourth transistors are configured to receive a clock signal.

Abstract: A phase-frequency detector (PFD) circuit that includes a binary phase detector and a ternary phase detector coupled to the binary phase detector. The binary phase detector is configured to, based on the PFD circuit being in a frequency acquisition state, compare a clock signal with a data signal and output up and down signals based on the comparison. The binary phase detector is also configured to be disabled based on the PFD circuit being in a frequency locked state. The ternary phase detector is configured to compare the clock signal with the data signal and output up, down, and hold signals based on the comparison.

Abstract: A phase detector and retimer circuit that includes a retimer circuit, a phase shift circuit coupled to the retimer circuit, and an error signal generation circuit coupled to the retimer circuit and the phase shift circuit. The retimer circuit is configured to receive a data signal and generate a first retimed data signal based on a first phase of a clock signal and a second retimed data signal based on a second phase of the clock signal. The phase shift circuit is configured to receive the data signal and phase shift the data signal to generate first, second, third, and fourth phase shifted data signals. The error signal generation circuit is configured to generate a first error signal and a second error signal based on the first and second retimed data signals and the first, second, third, and fourth phase shifted data signals.

Abstract: A loss of lock detector that includes a logic gate, a voltage-to-current converter coupled to the logic gate, a capacitor coupled to the converter, and a comparator coupled to the capacitor. The logic gate is configured to receive a first error signal and a second error signal from a phase detector, perform an AND function of the first and second error signals, and generate a gate output signal. The converter is configured to receive the gate output signal and generate a stream of current pulses representative of the gate output signal. The capacitor is configured to receive the stream of current pulses and generate a DC signal representative of the stream of current pulses. The comparator is configured to compare the DC signal to a reference signal and output a lock signal.

Abstract: A current mode logic (CML) latch that includes a first transistor coupled to a second transistor, a third transistor coupled to a fourth transistor, a first capacitor connected to the first, second, third, and fourth transistors, and a second capacitor cross-coupled with the first capacitor and connected to the third and fourth transistors. The first and second transistors are configured to receive a data signal. The third and fourth transistors are configured to receive a clock signal.

Abstract: A phase-frequency detector (PFD) circuit that includes a binary phase detector and a ternary phase detector coupled to the binary phase detector. The binary phase detector is configured to, based on the PFD circuit being in a frequency acquisition state, compare a clock signal with a data signal and output up and down signals based on the comparison. The binary phase detector is also configured to be disabled based on the PFD circuit being in a frequency locked state. The ternary phase detector is configured to compare the clock signal with the data signal and output up, down, and hold signals based on the comparison.

Abstract: An apparatus comprising: a first control switch driven by a first bit value; a first weighted switch driven by a first clock signal; a first intermediate node coupled between the first control switch and the second weighted switch; a first precharge transistor coupled to the first intermediate node, wherein the precharge transistor is driven by an inverse of the clock signal; a second control switch driven by an inverse of the bit; a second weighted switch driven by a second clock signal; a second intermediate node coupled between the second control switch and the second weighted switch; a second precharge transistor coupled to the second intermediate node, wherein the second precharge transistor is driven by an inverse of the second clock signal; and a capacitor coupled to the first control switch, the second control switch, the first precharge transistor and the second precharge transistor.

Abstract: An apparatus comprising: a first control switch driven by a first bit value; a first weighted switch driven by a first clock signal; a first intermediate node coupled between the first control switch and the second weighted switch; a first precharge transistor coupled to the first intermediate node, wherein the precharge transistor is driven by an inverse of the clock signal; a second control switch driven by an inverse of the bit; a second weighted switch driven by a second clock signal; a second intermediate node coupled between the second control switch and the second weighted switch; a second precharge transistor coupled to the second intermediate node, wherein the second precharge transistor is driven by an inverse of the second clock signal; and a capacitor coupled to the first control switch, the second control switch, the first precharge transistor and the second precharge transistor.

Abstract: Various systems, methods and apparatus for calibrating a clock generating circuit are discussed herein. As one example, a method for calibrating a voltage controlled oscillator is disclosed. The method includes fixing the control voltage of a fine tune capacitor in the voltage controlled oscillator at a predetermined level. A binary search is performed in a digital circuit for a value of a calibration word that is used to enable switched capacitors in a coarse tune capacitor bank in the voltage controlled oscillator. The calibration word is fixed at the value determined by the binary search, and the control voltage of the fine tune capacitor is released to enable adjustment of the control voltage by a feedback signal to the voltage controlled oscillator.

Abstract: Various systems, methods and apparatus for calibrating a clock generating circuit are discussed herein. As one example, a method for calibrating a voltage controlled oscillator is disclosed. The method includes fixing the control voltage of a fine tune capacitor in the voltage controlled oscillator at a predetermined level. A binary search is performed in a digital circuit for a value of a calibration word that is used to enable switched capacitors in a coarse tune capacitor bank in the voltage controlled oscillator. The calibration word is fixed at the value determined by the binary search, and the control voltage of the fine tune capacitor is released to enable adjustment of the control voltage by a feedback signal to the voltage controlled oscillator.

Abstract: A circuit takes a reference strobe signal as a first input, and a strobe ready signal generated from a memory that is strobed by the reference strobe signal as a second input. The circuit generates a self-timed strobe signal along with other control signals that are used to perform a subsequent memory access in a single clock cycle, thereby doubling memory access bandwidth.

Abstract: A circuit takes a reference strobe signal as a first input, and a strobe ready signal generated from a memory that is strobed by the reference strobe signal as a second input. The circuit generates a self-timed strobe signal along with other control signals that are used to perform a subsequent memory access in a single clock cycle, thereby doubling memory access bandwidth.