Patents by Inventor Mutsuhiko Yoshioka

Mutsuhiko Yoshioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7737707
    Abstract: A sheet-like probe and a method of producing the probe. In the probe electrode structure bodies do not come out from an insulation film and achieve high durability, and in a burn-in test for a wafer having a large area and for a circuit device having to-be-inspected electrodes with small intervals, positional displacement, caused by temperature variation, between the electrode structure bodies and the to-be-inspected electrode can be reliably prevented for stable connection conditions. The sheet-like probe includes an insulation layer and a contact film provided with electrode structure bodies arranged on the insulation layer to be apart from each other in the surface direction of the insulation layer and penetratingly extend in the thickness direction of the insulation layer. The electrode structure bodies each are composed of a surface electrode section exposed to the front surface of the insulation layer.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: June 15, 2010
    Assignee: JSR Corporation
    Inventors: Katsumi Sato, Kazuo Inoue, Hitoshi Fujiyama, Mutsuhiko Yoshioka, Hisao Igarashi
  • Patent number: 7671609
    Abstract: A sheet-like probe has a porous film. In the sheet-like probe, a contact film is penetratingly supported at each position of through-holes formed in the porous film, and a peripheral edge of the contact film and the porous film are integrated such that a flexible resin insulation layer is included in a fine hole of the porous film. Electrode structure bodies are supported in a penetrating manner in the insulation layer.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: March 2, 2010
    Assignee: JSR Corporation
    Inventors: Katsumi Sato, Kazuo Inoue, Hitoshi Fujiyama, Mutsuhiko Yoshioka, Hisao Igarashi
  • Patent number: 7656176
    Abstract: A probe member for wafer inspection having a sheet-like probe, the probe including a frame plate in which openings are formed, and contact films arranged on a front surface of the frame plate so as to close the openings, each of the contact films obtained by arranging, in an insulating film formed of a flexible resin, a plurality of electrode structures, and an anisotropically conductive connector, which is composed of a frame plate, in which a plurality of openings have been formed corresponding to the electrode regions, and a plurality of elastic anisotropically conductive films arranged on and supported by the frame plate so as to close the respective openings, wherein each of the openings of the frame plate in the sheet-like probe have a size for receiving the external shape in a plane direction in the elastic anisotropically conductive film of the anisotropically conductive connector.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: February 2, 2010
    Assignee: JSR Corporation
    Inventors: Mutsuhiko Yoshioka, Hitoshi Fujiyama, Hisao Igarashi
  • Publication number: 20090140756
    Abstract: Disclosed herein are a probe member for wafer inspection, a probe card for wafer inspection and a wafer inspection apparatus, by which a good electrically connected state can be surely achieved, positional deviation by temperature change can be prevented, and the good electrically connected state can be stably retained even when a wafer has a diameter of 8 inches or greater, and the pitch of electrodes to be inspected is extremely small.
    Type: Application
    Filed: October 27, 2005
    Publication date: June 4, 2009
    Applicant: JSR Corporation
    Inventors: Mutsuhiko Yoshioka, Hitoshi Fujiyama, Hisao Igarashi
  • Publication number: 20090015281
    Abstract: The method is a method for positioning a three-layered rectangular frame-like anisotropic conductive connector in order to inspect the electrical properties of an object for inspection. The positioning is carried out in the following manner. The three-layered anisotropic conductive sheet is composed of a first anisotropic conductive sheet, a center substrate and a second anisotropic conductive sheet. Markings and through-holes are formed on the center substrate, and semi-transparent protrusions and through-holes are formed on each of the first anisotropic conductive sheet and the second anisotropic conductive sheet.
    Type: Application
    Filed: July 10, 2008
    Publication date: January 15, 2009
    Applicants: JSR CORPORATION, TOKYO ELECTRON LIMITED
    Inventors: Mutsuhiko Yoshioka, Akira Matsuura, Masaya Naoi, Takashi Amemiya, Syuichi Tsukada, Tomohisa Hoshino
  • Publication number: 20070268032
    Abstract: Provided are a probe member, a probe card and a wafer inspection apparatus, by which a good electrically connected state can be surely achieved, positional deviation by temperature change can be prevented, and the good electrically connected state can be stably retained even when a wafer has a diameter of 8 inches or greater, and the pitch of electrodes to be inspected is extremely small.
    Type: Application
    Filed: November 10, 2005
    Publication date: November 22, 2007
    Applicant: JSR CORPORATION
    Inventors: Mutsuhiko Yoshioka, Hitoshi Fujiyama, Hisao Igarashi
  • Patent number: 7297360
    Abstract: An insulation film comprising an organosilicon polymer and an organic polymer such as polyarylene, polyarylene ether, polyimide, and fluororesin is disclosed, wherein the organosilicon polymer has a relative dielectric constant of 4 or less and has a dry etching selection ratio of 1/3 or less to silicon oxide, fluorine-doped silicon oxide, organosilicate glass, carbon-doped silicon oxide, methyl silsesquioxane, hydrogen silsesquioxane, a spin-on-glass, or polyorganosiloxane. The insulation film is used as an etching stopper or a hard mask in a dry etching process of interlayer dielectric films for semiconductors and can produce semiconductors having excellent precision with minimal damages.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: November 20, 2007
    Assignee: JSR Corporation
    Inventors: Mutsuhiko Yoshioka, Eiji Hayashi, Kouji Sumiya, Atsushi Shiota
  • Publication number: 20070205783
    Abstract: A sheet-like probe and a method of producing the probe. In the probe electrode structure bodies do not come out from an insulation film and achieve high durability, and in a burn-in test for a wafer having a large area and for a circuit device having to-be-inspected electrodes with small intervals, positional displacement, caused by temperature variation, between the electrode structure bodies and the to-be-inspected electrode can be reliably prevented for stable connection conditions. The sheet-like probe includes an insulation layer and a contact film provided with electrode structure bodies arranged on the insulation layer to be apart from each other in the surface direction of the insulation layer and penetratingly extend in the thickness direction of the insulation layer. The electrode structure bodies each are composed of a surface electrode section exposed to the front surface of the insulation layer.
    Type: Application
    Filed: April 26, 2005
    Publication date: September 6, 2007
    Applicant: JSR CORPORATION
    Inventors: Katsumi Sato, Kazuo Inoue, Hitoshi Fujiyama, Mutsuhiko Yoshioka, Hisao Igarashi
  • Publication number: 20070151951
    Abstract: A stopper for chemical mechanical planarization comprising an organosilicon polymer, in particular a polycarbosilane, is provided. The stopper used for polishing wafers with a wiring pattern in the manufacture of semiconductor devices to protect interlayer dielectric films made of a material such as SiO2, fluorine dope SiO2, or organic or inorganic SOG (Spin-on glass) from damages during the chemical mechanical planarization process.
    Type: Application
    Filed: February 28, 2007
    Publication date: July 5, 2007
    Applicant: JSR Corporation
    Inventors: Mutsuhiko Yoshioka, Eiji Hayashi, Norihiko Ikeda
  • Patent number: 7189651
    Abstract: A stopper for chemical mechanical planarization comprising an organosilicon polymer, in particular a polycarbosilane, is provided. The stopper used for polishing wafers with a wiring pattern in the manufacture of semiconductor devices to protect interlayer dielectric films made of a material such as SiO2, fluorine dope SiO2, or organic or inorganic SOG (Spin-on glass) from damages during the chemical mechanical planarization process.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: March 13, 2007
    Assignee: JSR Corporation
    Inventors: Mutsuhiko Yoshioka, Eiji Hayashi, Norihiko Ikeda
  • Publication number: 20060252044
    Abstract: There are provided a biochip and a biochip kit, in which a target contained in an analyte is reacted with a probe with high efficiency in a short time, B/F separation efficiency is high, and high-sensitive quantitative determination and detection can be realized, and a production process thereof, and a method for reacting a target contained in an analyte with a probe, and, for example, separation and fractionation method and a detection and identification method for a target contained in an analyte, using the biochip kit. The biochip according to the present invention comprises a well(s) provided with a filter comprising straight pores, with a uniform pore diameter, provided at uniform pore spacings. A dispersion with probe-supported particles dispersed therein is contained in the well, and an analyte is placed in the well(s) to react the analyte with the probe-supported particles. A solution such as an analyte solution can be introduced into or discharged from the well through the filter.
    Type: Application
    Filed: April 23, 2004
    Publication date: November 9, 2006
    Applicant: JSR Corporation
    Inventors: Katsuya Okumura, Makoto Mihara, Mutsuhiko Yoshioka
  • Patent number: 6890605
    Abstract: An insulating film for semiconductors which has excellent adhesion to films formed by CVD and is useful as a dielectric film in semiconductor devices and the like is provided.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: May 10, 2005
    Assignee: JSR Corporation
    Inventors: Michinori Nishikawa, Manabu Sekiguchi, Matthias Patz, Mutsuhiko Yoshioka, Atsushi Shiota, Kinji Yamada
  • Publication number: 20040110896
    Abstract: An insulation film comprising an organosilicon polymer and an organic polymer such as polyarylene, polyarylene ether, polyimide, and fluororesin is disclosed, wherein the organosilicon polymer has a relative dielectric constant of 4 or less and has a dry etching selection ratio of 1/3 or less to silicon oxide, fluorine-doped silicon oxide, organosilicate glass, carbon-doped silicon oxide, methyl silsesquioxane, hydrogen silsesquioxane, a spin-on-glass, or polyorganosiloxane. The insulation film is used as an etching stopper or a hard mask in a dry etching process of interlayer dielectric films for semiconductors and can produce semiconductors having excellent precision with minimal damages.
    Type: Application
    Filed: December 4, 2003
    Publication date: June 10, 2004
    Applicant: JSR Corporation
    Inventors: Mutsuhiko Yoshioka, Eiji Hayashi, Kouji Sumiya, Atsushi Shiota
  • Publication number: 20040110379
    Abstract: A stopper for chemical mechanical planarization comprising an organosilicon polymer, in particular a polycarbosilane, is provided. The stopper used for polishing wafers with a wiring pattern in the manufacture of semiconductor devices to protect interlayer dielectric films made of a material such as SiO2, fluorine dope SiO2, or organic or inorganic SOG (Spin-on glass) from damages during the chemical mechanical planarization process.
    Type: Application
    Filed: December 4, 2003
    Publication date: June 10, 2004
    Applicant: JSR Corporation
    Inventors: Mutsuhiko Yoshioka, Eiji Hayashi, Norihiko Ikeda
  • Patent number: 6645881
    Abstract: A coating solution for used in a scan coating method contains a low vapor pressure solvent having a vapor pressure lower than 1 Torr (133.322 Pa) at room temperature.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: November 11, 2003
    Assignees: Kabushiki Kaisha Toshiba, JSR Corporation
    Inventors: Nobuhide Yamada, Rempei Nakata, Makoto Sugiura, Mutsuhiko Yoshioka, Takahiro Kitano, Shinji Kobayashi
  • Publication number: 20030139063
    Abstract: A coating solution for used in a scan coating method contains a low vapor pressure solvent having a vapor pressure lower than 1 Torr (133.322 Pa) at room temperature.
    Type: Application
    Filed: April 2, 2002
    Publication date: July 24, 2003
    Inventors: Nobuhide Yamada, Rempei Nakata, Makoto Sugiura, Mutsuhiko Yoshioka, Takahiro Kitano, Shinji Kobayashi
  • Publication number: 20030059550
    Abstract: An insulating film for semiconductors which has excellent adhesion to films formed by CVD and is useful as a dielectric film in semiconductor devices and the like is provided.
    Type: Application
    Filed: September 24, 2002
    Publication date: March 27, 2003
    Applicant: JSR CORPORATION
    Inventors: Michinori Nishikawa, Manabu Sekiguchi, Matthias Patz, Mutsuhiko Yoshioka, Atsushi Shiota, Kinji Yamada