Abstract: Provided is a comparator configured to compare input voltages, which are input to a first dynamic comparator and a second dynamic comparator, with a reference voltage, select either an output signal of the first dynamic comparator or an output signal of the second dynamic comparator based on the comparison result, output the selected output signal, and control clock signals, which are input to the first dynamic comparator and the second dynamic comparator respectively, based on the comparison result, so as to stop the operation of the dynamic comparator of which output signal is not selected.

Abstract: Provided is a comparator configured to compare input voltages, which are input to a first dynamic comparator and a second dynamic comparator, with a reference voltage, select either an output signal of the first dynamic comparator or an output signal of the second dynamic comparator based on the comparison result, output the selected output signal, and control clock signals, which are input to the first dynamic comparator and the second dynamic comparator respectively, based on the comparison result, so as to stop the operation of the dynamic comparator of which output signal is not selected.

Abstract: A D/A converter of switched capacitor type capable of shortening the time for D/A conversion process without increasing power consumption is provided. The D/A converter comprises capacitors Cx and Cy for receiving input voltage corresponding to the digital data and charging the amount of charge corresponding to the input voltage, and an operational amplifier A21 including a first amplified output terminal To1 and a second amplified output terminal To2 for individually outputting amplified signals generated based on a signal inputted to the input terminal. During the conversion process, the amplified signal is outputted from the first amplified output terminal To1, after the conversion process is completed, the amplified signal is outputted through an output switch Sw6 from the first amplified output terminal To2.

Abstract: A D/A converter of switched capacitor type capable of shortening the time for D/A conversion process without increasing power consumption is provided. The D/A converter comprises capacitors Cx and Cy for receiving input voltage corresponding to the digital data and charging the amount of charge corresponding to the input voltage, and an operational amplifier A21 including a first amplified output terminal To1 and a second amplified output terminal To2 for individually outputting amplified signals generated based on a signal inputted to the input terminal. During the conversion process, the amplified signal is outputted from the first amplified output terminal To1, after the conversion process is completed, the amplified signal is outputted through an output switch Sw6 from the first amplified output terminal To2.

Abstract: An arithmetic circuit includes a sample hold portion, an adding portion, a subtracting portion, an A/D sub-converter and a D/A sub-converter. The adding portion adds first and second residual voltages provided from a preceding stage. In a first hold mode, the subtracting portion subtracts an analog voltage from a voltage produced by the addition by the adding portion, and provides a voltage produced by the subtraction as a first residual voltage in this stage to a next stage. In a second hold mode, the subtracting portion interchanges internal capacitors with each other, subtracts the analog voltage from a voltage produced by the addition by the adding portion, and provides a voltage produced by the subtraction as a second residual voltage to the next stage.

Abstract: An arithmetic circuit includes a sample hold portion, an adding portion, a subtracting portion, an A/D sub-converter and a D/A sub-converter. The adding portion adds first and second residual voltages provided from a preceding stage. In a first hold mode, the subtracting portion subtracts an analog voltage from a voltage produced by the addition by the adding portion, and provides a voltage produced by the subtraction as a first residual voltage in this stage to a next stage. In a second hold mode, the subtracting portion interchanges internal capacitors with each other, subtracts the analog voltage from a voltage produced by the addition by the adding portion, and provides a voltage produced by the subtraction as a second residual voltage to the next stage.