Patents by Inventor Mutsuo Hidaka

Mutsuo Hidaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11362257
    Abstract: A quantum bit device according to the present invention includes a first quantum bit substrate 10 which includes a first superconductive wiring 13 disposed to have a magnetically coupled portion with a first superconductive magnetic flux quantum bit 14 on a surface thereof, a second quantum bit substrate 11 which includes a second superconductive wiring 13 disposed to have a magnetically coupled portion with a second superconductive magnetic flux quantum bit 14 on a surface thereof, and a base substrate 12 which includes a third superconductive wiring 13 configured by two superconductive wirings extending parallel to each other on a surface thereof.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: June 14, 2022
    Inventors: Mutsuo Hidaka, Masaaki Maezawa
  • Publication number: 20210167271
    Abstract: A quantum bit device according to the present invention includes a first quantum bit substrate 10 which includes a first superconductive wiring 13 disposed to have a magnetically coupled portion with a first superconductive magnetic flux quantum bit 14 on a surface thereof, a second quantum bit substrate 11 which includes a second superconductive wiring 13 disposed to have a magnetically coupled portion with a second superconductive magnetic flux quantum bit 14 on a surface thereof, and a base substrate 12 which includes a third superconductive wiring 13 configured by two superconductive wirings extending parallel to each other on a surface thereof.
    Type: Application
    Filed: May 9, 2018
    Publication date: June 3, 2021
    Inventors: Mutsuo HIDAKA, Masaaki MAEZAWA
  • Patent number: 7505310
    Abstract: In a superconducting random access memory according to this invention, drive lines such as a word line and a bit line, and a sense line for accessing a memory cell array are each divided into a plurality of blocks and an in-block signal propagation circuit having a level-logic drive circuit and sense circuit each with high load drive capability is used for signal propagation in each of the blocks. Further, for long-distance signal propagation between the blocks, superconducting passive transmission lines formed by single flux quantum (SFQ) devices and capable of high-speed operation are used. As a result, the high-speed operation as a whole is enabled. It is possible to additionally use splitters or confluence buffers and latch circuits and, further, a binary tree structure may be adopted.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: March 17, 2009
    Assignee: NEC Corporation
    Inventors: Shuuichi Nagasawa, Mutsuo Hidaka, Keiichi Tanabe
  • Publication number: 20060255987
    Abstract: In a superconducting random access memory according to this invention, drive lines such as a word line and a bit line, and a sense line for accessing a memory cell array are each divided into a plurality of blocks and an in-block signal propagation circuit having a level-logic drive circuit and sense circuit each with high load drive capability is used for signal propagation in each of the blocks. Further, for long-distance signal propagation between the blocks, superconducting passive transmission lines formed by single flux quantum (SFQ) devices and capable of high-speed operation are used. As a result, the high-speed operation as a whole is enabled. It is possible to additionally use splitters or confluence buffers and latch circuits and, further, a binary tree structure may be adopted.
    Type: Application
    Filed: March 14, 2006
    Publication date: November 16, 2006
    Inventors: Shuuichi Nagasawa, Mutsuo Hidaka, Keiichi Tanabe
  • Patent number: 7081417
    Abstract: To provide a planarization method which does not depend upon the size and the density of a wiring pattern and in which a reliable wiring system and a Josephson device can be formed and wiring structure, an insulation layer is planarized by forming a reversal pattern mask of wiring and selectively removing the insulation layer on the wiring.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: July 25, 2006
    Assignees: Hitachi, Ltd., NEC Corporation, International Superconductivity Technology Center, the Judicial Foundation
    Inventors: Kenji Hinode, Shuichi Nagasawa, Yoshihiro Kitagawa, Mutsuo Hidaka, Keiichi Tanabe
  • Patent number: 6922066
    Abstract: In a sampler for use in measuring a waveform of an electric signal, a measurement target current is given as the electric signal to a sampler chip 11 and is also used to produce a trigger current Itr for determining measurement timing on the sampler chip. A comparator 20 compares a sum of a feedback current, a current derived from the measurement target current, and the trigger current Itr with a threshold value to produce an SFQ pulse when the sum exceeds the threshold value. The SFQ pulse produced by the comparator is observed or counted for a predetermined duration to measure the waveform of the electric signal.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: July 26, 2005
    Assignees: NEC Corporation, International Superconductivity Technology Center
    Inventor: Mutsuo Hidaka
  • Publication number: 20040266209
    Abstract: To provide a planarization method which does not depend upon the size and the density of a wiring pattern and in which a reliable wiring system and a Josephson device can be formed and wiring structure, an insulation layer is planarized by forming a reversal pattern mask of wiring and selectively removing the insulation layer on the wiring.
    Type: Application
    Filed: June 24, 2004
    Publication date: December 30, 2004
    Inventors: Kenji Hinode, Shuichi Nagasawa, Yoshihiro Kitagawa, Mutsuo Hidaka, Keiichi Tanabe
  • Publication number: 20030028338
    Abstract: In a sampler for use in measuring a waveform of an electric signal, a measurement target current is given as the electric signal to a sampler chip 11 and is also used to produce a trigger current Itr for determining measurement timing on the sampler chip. A comparator 20 compares a sum of a feedback current, a current derived from the measurement target current, and the trigger current Itr with a threshold value to produce an SFQ pulse when the sum exceeds the threshold value. The SFQ pulse produced by the comparator is observed or counted for a predetermined duration to measure the waveform of the electric signal.
    Type: Application
    Filed: July 16, 2002
    Publication date: February 6, 2003
    Applicant: NEC CORPORATION
    Inventor: Mutsuo Hidaka
  • Patent number: 6320369
    Abstract: A superconducting current measuring circuit is provided with a detection loop through which a current flows by the influence of a magnetic field generated by a measurement target current. The detection loop contains a superconductor. The superconducting current measuring circuit is also provided with a superconducting sampler circuit for measuring the current flowing through the detection loop.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: November 20, 2001
    Assignee: NEC Corporation
    Inventors: Mutsuo Hidaka, Shuichi Tahara
  • Patent number: 5019551
    Abstract: In a superconducting contact structure between an oxide superconductor and a metal superconductor, the oxide superconductor has a recess in a surface which is in contact with the metal superconductor.
    Type: Grant
    Filed: September 6, 1988
    Date of Patent: May 28, 1991
    Assignee: NEC Corporation
    Inventor: Mutsuo Hidaka