Patents by Inventor Mutsuo Tsuji
Mutsuo Tsuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230215830Abstract: When a semiconductor element and a wiring board are connected to each other, connection at a minute pitch is performed while securing reliability. In a semiconductor device, a semiconductor element and a wiring board are connected to each other. A bump is formed on an electrode in either the semiconductor element or the wiring board. This bump contains metal nanoparticles as a component. The bump may be formed by sintering the metal nanoparticles that are applied. Furthermore, the metal nanoparticles may be applied and sintered a plurality of times to form a plurality of layers. A connection between the semiconductor element and the wiring board may be formed by sintering the other metal nanoparticles that are applied.Type: ApplicationFiled: March 23, 2021Publication date: July 6, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Mutsuo TSUJI
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Publication number: 20220415937Abstract: Alignment accuracy between an imaging element and a filming lens is improved. An imaging apparatus includes an imaging element, a wiring substrate, a sealing section, and fitting sections. The imaging element includes an imaging chip and pads. A light transmission section that transmits incident light is arranged on the imaging chip, and the imaging chip generates an image signal on the basis of the incident light that has transmitted through the light transmission section. The pads are arranged on a bottom surface of the imaging chip which is a surface different from the surface on which the light transmission section is arranged and convey the generated image signal. The wiring substrate includes wiring that is connected to the pads, and the imaging element is arranged on a front surface of the wiring substrate. The sealing section is arranged adjacent to side surfaces of the imaging chip which are the surfaces adjacent to the bottom surface of the imaging chip and seals the imaging chip.Type: ApplicationFiled: September 30, 2020Publication date: December 29, 2022Inventors: MUTSUO TSUJI, DAISUKE CHINO
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Patent number: 7367120Abstract: A method of manufacturing a solid-state imaging device. An end portion on the aperture side of each of the plurality of wirings forms an internal terminal portion and an end portion on the outer peripheral side of each of the plurality of wirings forms an external terminal portion, the internal terminal portion of the wiring being connected electrically with an electrode of the imaging element. The wirings are made of thin metal plate leads, the base is made up of a resin molded member in which the thin metal plate leads are embedded, and at least a part of a side edge face of the thin metal plate leads is embedded in the base. The rigidity of the base is enhanced by the thin metal plate leads, thus reducing a curl and a warp of the base.Type: GrantFiled: November 14, 2006Date of Patent: May 6, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masanori Minamio, Mutsuo Tsuji, Kouichi Yamauchi
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Publication number: 20070069319Abstract: A solid-state imaging device includes: a base made of an insulation material and having a frame form in planar shape with an aperture formed at an inner region; a plurality of wirings provided on one surface of the base and extending toward an outer periphery of the base from a region along the aperture; and an imaging element mounted on the surface of the base with wirings provided thereon so that a light-receptive region of the imaging element faces the aperture. An end portion on the aperture side of each of the plurality of wirings forms an internal terminal portion and an end portion on the outer peripheral side of each of the plurality of wirings forms an external terminal portion, the internal terminal portion of the wiring being connected electrically with an electrode of the imaging element.Type: ApplicationFiled: November 14, 2006Publication date: March 29, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masanori Minamio, Mutsuo Tsuji, Kouichi Yamauchi
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Patent number: 7154156Abstract: A solid-state imaging device includes: a base made of an insulation material and having a frame form in planar shape with an aperture formed at an inner region; a plurality of wirings provided on one surface of the base and extending toward an outer periphery of the base from a region along the aperture; and an imaging element mounted on the surface of the base with wirings provided thereon so that a light-receptive region of the imaging element faces the aperture. An end portion on the aperture side of each of the plurality of wirings forms an internal terminal portion and an end portion on the outer peripheral side of each of the plurality of wirings forms an external terminal portion, the internal terminal portion of the wiring being connected electrically with an electrode of the imaging element.Type: GrantFiled: September 30, 2003Date of Patent: December 26, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masanori Minamio, Mutsuo Tsuji, Kouichi Yamauchi
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Publication number: 20060208349Abstract: A semiconductor device and a manufacturing method for the same are provided wherein the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can be improved in the case wherein the second semiconductor chip, which is located above the lower, first semiconductor chip, is significantly larger than the first semiconductor chip in a configuration wherein two semiconductor chips are stacked and mounted on a wiring board. In this semiconductor device the rear surface of the first semiconductor chip and the rear surface of the second semiconductor chip are adhered to each other by means of adhesive and the side of the adhesive is inclined from the edge portions of the first semiconductor chip toward the portions of the second semiconductor chip extending from the side of the first semiconductor chip.Type: ApplicationFiled: March 30, 2006Publication date: September 21, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Toshiyuki Fukuda, Hiroaki Fujimoto, Mutsuo Tsuji, Takashi Yui, Yoshiaki Takeoka
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Patent number: 7087455Abstract: A semiconductor device and a manufacturing method for the same are provided wherein the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can be improved in the case wherein the second semiconductor chip, which is located above the lower, first semiconductor chip, is significantly larger than the first semiconductor chip in a configuration wherein two semiconductor chips are stacked and mounted on a wiring board. In this semiconductor device the rear surface of the first semiconductor chip and the rear surface of the second semiconductor chip are adhered to each other by means of adhesive and the side of the adhesive is inclined from the edge portions of the first semiconductor chip toward the portions of the second semiconductor chip extending from the side of the first semiconductor chip.Type: GrantFiled: August 8, 2003Date of Patent: August 8, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshiyuki Fukuda, Hiroaki Fujimoto, Mutsuo Tsuji, Takashi Yui, Yoshiaki Takeoka
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Publication number: 20060079023Abstract: A semiconductor device and a manufacturing method for the same are provided wherein the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can be improved in the case wherein the second semiconductor chip, which is located above the lower, first semiconductor chip, is significantly larger than the first semiconductor chip in a configuration wherein two semiconductor chips are stacked and mounted on a wiring board. In this semiconductor device the rear surface of the first semiconductor chip and the rear surface of the second semiconductor chip are adhered to each other by means of adhesive and the side of the adhesive is inclined from the edge portions of the first semiconductor chip toward the portions of the second semiconductor chip extending from the side of the first semiconductor chip.Type: ApplicationFiled: November 18, 2005Publication date: April 13, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Toshiyuki Fukuda, Hiroaki Fujimoto, Mutsuo Tsuji, Takashi Yui, Yoshiaki Takeoka
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Publication number: 20040211986Abstract: A solid-state imaging device includes: a base made of an insulation material and having a frame form in planar shape with an aperture formed at an inner region; a plurality of wirings provided on one surface of the base and extending toward an outer periphery of the base from a region along the aperture; and an imaging element mounted on the surface of the base with wirings provided thereon so that a light-receptive region of the imaging element faces the aperture. An end portion on the aperture side of each of the plurality of wirings forms an internal terminal portion and an end portion on the outer peripheral side of each of the plurality of wirings forms an external terminal portion, the internal terminal portion of the wiring being connected electrically with an electrode of the imaging element.Type: ApplicationFiled: September 30, 2003Publication date: October 28, 2004Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Masanori Minamio, Mutsuo Tsuji, Kouichi Yamauchi
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Publication number: 20040145040Abstract: A semiconductor device and a manufacturing method for the same are provided wherein the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can be improved in the case wherein the second semiconductor chip, which is located above the lower, first semiconductor chip, is significantly larger than the first semiconductor chip in a configuration wherein two semiconductor chips are stacked and mounted on a wiring board. In this semiconductor device the rear surface of the first semiconductor chip and the rear surface of the second semiconductor chip are adhered to each other by means of adhesive and the side of the adhesive is inclined from the edge portions of the first semiconductor chip toward the portions of the second semiconductor chip extending from the side of the first semiconductor chip.Type: ApplicationFiled: August 8, 2003Publication date: July 29, 2004Inventors: Toshiyuki Fukuda, Hiroaki Fujimoto, Mutsuo Tsuji, Takashi Yui, Yoshiaki Takeoka
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Patent number: 5264726Abstract: In a chip-carrier provided with a chip-carrier substrate, a chip-carrier cover and an IC chip, said IC chip being arranged at a distance from a circuit surface of the IC chip being directed toward the chip-carrier substrate, an .alpha.-ray shielding film made of film material containing few radioactive elements, and adhered to a surface of the chip-carrier substrate facing the IC chip or to the circuit surface of the IC chip is provided for protecting the IC chip from the IC chip.Type: GrantFiled: October 16, 1992Date of Patent: November 23, 1993Assignee: NEC CorporationInventors: Yukio Yamaguchi, Mutsuo Tsuji
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Patent number: 4855869Abstract: A chip carrier including a substrate having a plurality of pads formed on the upper and lower surfaces thereof and wirings to connect the pads. The chip carrier also includes an integrated circuit chip having a plurality of leads connected to corresponding ones of the pads. A first metal frame is included which is soldered to the upper surface of the substrate so as to surround the integrated circuit chip. The chip carrier also includes a second metal frame which is seam-welded to the upper end of the first metal frame so as to surround the integrated circuit chip and a plate is soldered to the upper end of the second metal frame so as to cover the integrated circuit chip.Type: GrantFiled: September 18, 1987Date of Patent: August 8, 1989Assignee: NEC CorporationInventor: Mutsuo Tsuji
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Patent number: 4748538Abstract: A semiconductor module includes a multi-layer wiring substrate provided at a first surface with a plurality of input/output terminals and at a second surface with lead terminals connected to the input/output terminals. A cap is provided above the multi-layer wiring substrate by means of leg members which forms a space between the cap and the multi-layer wiring substrate. A semiconductor chip is fixed to the side exposed to the space of the cap, and lead wires are provided, each having one end attached to a terminal of the semiconductor chip. The lead wires are drawn out in advance so that they can be visually confirmed from an upper direction of the cap and have their other ends connected to the lead terminals.Type: GrantFiled: July 3, 1986Date of Patent: May 31, 1988Assignee: NEC CorporationInventor: Mutsuo Tsuji
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Patent number: D505964Type: GrantFiled: December 3, 2003Date of Patent: June 7, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masanori Minamio, Yoshinobu Kunitomo, Mutsuo Tsuji, Koichi Yamauchi