Patents by Inventor Myeong-o Kim
Myeong-o Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10635531Abstract: An error correction circuit of a semiconductor memory device including a memory cell array includes an error correction code (ECC) memory that stores an ECC and an ECC engine. The ECC is represented by a generation matrix. The ECC engine generates first parity data based on main data using the ECC, and corrects at least one error bit in the main data read from the memory cell array using the first parity data. The main data includes a plurality of data bits divided into a plurality of sub codeword groups. The ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub codeword groups. The column vectors have elements configured to restrict a location of a sub codeword group in which a mis-corrected bit occurs, in which the mis-corrected bit is generated due to error bits in the main data.Type: GrantFiled: January 12, 2018Date of Patent: April 28, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Uhn Cha, Myeong-O Kim
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Patent number: 10503589Abstract: Semiconductor memory device may include a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The control logic circuit may, in a first write operation mode, control the I/O gating circuit to select a sub-page, read a first unit of data including a first sub unit of data, a second sub unit of data and a first parity data from the sub-page, and provide the first unit of data to the error correction circuit. The control logic circuit may also control the error correction circuit to perform an error-correcting code decoding on the first unit of data to generate syndrome data, generate second parity data based on a portion of the first unit of data and generate third parity data based on a write parity data, the second parity data and the syndrome data.Type: GrantFiled: June 29, 2018Date of Patent: December 10, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Uhn Cha, Myeong-O Kim, In-Woo Jun
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Publication number: 20190146870Abstract: Semiconductor memory device may include a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The control logic circuit may, in a first write operation mode, control the I/O gating circuit to select a sub-page, read a first unit of data including a first sub unit of data, a second sub unit of data and a first parity data from the sub-page, and provide the first unit of data to the error correction circuit. The control logic circuit may also control the error correction circuit to perform an error-correcting code decoding on the first unit of data to generate syndrome data, generate second parity data based on a portion of the first unit of data and generate third parity data based on a write parity data, the second parity data and the syndrome data.Type: ApplicationFiled: June 29, 2018Publication date: May 16, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Uhn CHA, Myeong-O KIM, In-Woo JUN
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Publication number: 20190012229Abstract: An error correction circuit of a semiconductor memory device including a memory cell array includes an error correction code (ECC) memory that stores an ECC and an ECC engine. The ECC is represented by a generation matrix. The ECC engine generates first parity data based on main data using the ECC, and corrects at least one error bit in the main data read from. the memory cell array using the first parity data. The main data includes a plurality of data bits divided into a plurality of sub codeword groups. The ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub codeword groups. The column vectors have elements configured to restrict a location of a sub codeword group in which a mis-corrected bit occurs, in which the mis-corrected bit is generated due to error bits in the main data.Type: ApplicationFiled: January 12, 2018Publication date: January 10, 2019Inventors: SANG-UHN CHA, Myeong-O KIM
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Patent number: 9508452Abstract: A partial chip and a system including the partial chip are provided. The partial chip includes a memory cell array and a signal control circuit. The memory cell array includes a pass region and a fail region. The signal control circuit is configured to generate second data corresponding to first data to be output from the fail region.Type: GrantFiled: January 23, 2015Date of Patent: November 29, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young Seok Ryu, Myeong O Kim
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Patent number: 9460766Abstract: A memory device may include a pre-charge control circuit, an active control circuit, and a driver circuit. The pre-charge control circuit may be configured to receive an active command after receiving a pre-charge command for a first bank, determine whether or not a pre-charge operation for the first bank has ended when receiving the active command, and generate an active instruction signal according to a result of the determination. The active control circuit may be configured to generate an active control signal for an active operation according to the active instruction signal. The driver circuit may be configured to control an active operation according to the active control signal.Type: GrantFiled: July 16, 2015Date of Patent: October 4, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Yoon Lee, Myeong-O Kim, Kyo-Min Sohn, Sang-Joon Hwang
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Publication number: 20160071561Abstract: A memory device may include a pre-charge control circuit, an active control circuit, and a driver circuit. The pre-charge control circuit may be configured to receive an active command after receiving a pre-charge command for a first bank, determine whether or not a pre-charge operation for the first bank has ended when receiving the active command, and generate an active instruction signal according to a result of the determination. The active control circuit may be configured to generate an active control signal for an active operation according to the active instruction signal. The driver circuit may be configured to control an active operation according to the active control signal.Type: ApplicationFiled: July 16, 2015Publication date: March 10, 2016Inventors: Tae-Yoon LEE, Myeong-O KIM, Kyo-Min SOHN, Sang-Joon HWANG
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Patent number: 9171605Abstract: Provided is a method of detecting a concentrated address of a semiconductor device using an n-bit address. The method includes dividing the n-bit address into k groups, wherein each of n and k is an integer equal to or greater than 2, for each group of the k groups, detecting one or more concentrated sub addresses corresponding to the group, and generating at least one concentrated address by combining the one or more concentrated sub addresses for the k groups.Type: GrantFiled: December 11, 2013Date of Patent: October 27, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Sik Kim, Won-Il Bae, Myeong-O Kim, Min-Soo Kim, Ho-Seok Seol, Min-Sang Park, Kyo-Min Sohn, Chi-Hwan Lee, Sang-Joon Hwang
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Publication number: 20150206573Abstract: A partial chip and a system including the partial chip are provided. The partial chip includes a memory cell array and a signal control circuit. The memory cell array includes a pass region and a fail region. The signal control circuit is configured to generate second data corresponding to first data to be output from the fail region.Type: ApplicationFiled: January 23, 2015Publication date: July 23, 2015Inventors: YOUNG SEOK RYU, Myeong O Kim
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Patent number: 8416632Abstract: A bitline precharge voltage generator comprises a leakage trimming unit and a bitline precharge voltage providing unit. The leakage trimming unit applies a leakage current to an output node to place a bitline precharge voltage at an edge of a dead zone. The bitline precharge voltage providing unit provides the bitline precharge voltage to the output node, and sets the bitline precharge voltage to a target level. The bitline precharge voltage generator generates the bitline precharge voltage having a distribution including the dead zone.Type: GrantFiled: October 14, 2010Date of Patent: April 9, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Heung Kim, Seong-Jin Jang, Myeong-O Kim, Hong-Jun Lee, Tae-Yoon Lee
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Patent number: 8107308Abstract: A semiconductor memory device is provided. A memory cell array has a plurality of memory cells connected between a plurality of word lines and a plurality of bit-line pairs. A sense amplifier unit has a plurality of sense amplifiers connected with the bit-line pairs respectively and amplifies data of the bit-line pairs to a sensing voltage level. A command decoder decodes a command applied from the outside and outputs the decoded command. A plurality of input/output (I/O) gates electrically connects the bit-line pairs with corresponding I/O line pairs in response to a voltage level applied through a plurality of corresponding column selection lines. A column decoder decodes a column address and drives at least one of the column selection lines to a plurality of different voltages levels.Type: GrantFiled: January 12, 2010Date of Patent: January 31, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Myeong-O Kim, Jae-Won Ko, Reum Oh
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Publication number: 20110122711Abstract: A bitline precharge voltage generator comprises a leakage trimming unit and a bitline precharge voltage providing unit. The leakage trimming unit applies a leakage current to an output node to place a bitline precharge voltage at an edge of a dead zone. The bitline precharge voltage providing unit provides the bitline precharge voltage to the output node, and sets the bitline precharge voltage to a target level. The bitline precharge voltage generator generates the bitline precharge voltage having a distribution including the dead zone.Type: ApplicationFiled: October 14, 2010Publication date: May 26, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-Heung KIM, Seong-Jin JANG, Myeong-O KIM, Hong-Jun LEE, Tae-Yoon LEE
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Patent number: 7872932Abstract: A method and semiconductor memory device for precharging a local input/output line. The semiconductor memory device, which may have an open bit line structure, transmits data through local input/output lines that are coupled to bit lines of first to n-th memory cell array blocks (n being a natural number). The semiconductor memory device may include a precharge unit configured to generate a plurality of precharge signals and a controller configured to control precharging of the at least one local input/output line responsive to block information corresponding to activation of at least one of the memory cell array blocks and responsive to at least one of the precharge signals.Type: GrantFiled: August 6, 2008Date of Patent: January 18, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Myeong-O Kim, Byung-Chul Kim, Yong-Gyu Chu
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Publication number: 20100177582Abstract: A semiconductor memory device is provided. A memory cell array has a plurality of memory cells connected between a plurality of word lines and a plurality of bit-line pairs. A sense amplifier unit has a plurality of sense amplifiers connected with the bit-line pairs respectively and amplifies data of the bit-line pairs to a sensing voltage level. A command decoder decodes a command applied from the outside and outputs the decoded command. A plurality of input/output (I/O) gates electrically connects the bit-line pairs with corresponding I/O line pairs in response to a voltage level applied through a plurality of corresponding column selection lines. A column decoder decodes a column address and drives at least one of the column selection lines to a plurality of different voltages levels.Type: ApplicationFiled: January 12, 2010Publication date: July 15, 2010Inventors: Myeong-O Kim, Jae-Won Ko, Reum Oh
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Patent number: 7652942Abstract: A sense amplifier includes a reference signal providing unit and an internal sense amplification unit. The reference signal providing unit provides a reference bit line signal in response to a reference control signal. The internal sense amplification unit receives the reference bit line signal and data signals that correspond to the data. The received signals are provided through bit lines connected to the memory cell array. The internal sense amplification unit senses the received reference bit line signal and the data signals and amplifies the sensed signals. The sense amplifier senses data stored in memory cells connected to dummy bit lines of the outmost memory cell array of a semiconductor memory device such that the memory cells that are not used can be used. Accordingly, the design area and cost of the semiconductor memory device can be reduced.Type: GrantFiled: June 1, 2007Date of Patent: January 26, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Myeong-o Kim, Yun-sang Lee
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Patent number: 7643364Abstract: A semiconductor memory device including a bit line sense amplifier for amplifying a voltage corresponding to a charge stored in a capacitor of a memory cell and outputting an amplified voltage and an I/O sense amplifier for receiving the output of the bit line sense amplifier, amplifying a voltage level of the output and outputting an amplified voltage level is disclosed.Type: GrantFiled: December 20, 2007Date of Patent: January 5, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Cheol Lee, Myeong-O Kim
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Patent number: 7570529Abstract: A sense amplifier circuit of a semiconductor memory device and a method of operating the same, in which the sense amplifier circuit includes a bit line sense amplifier connected with a bit line to sense and amplify a signal of the bit line, and a calibration circuit calibrating a voltage level of the bit line based on a logic threshold value of the bit line sense amplifier. The bit line sense amplifier senses and amplifies the signal of the bit line after the voltage level of the bit line is calibrated. The bit line sense amplifier may include a 2-stage cascade latch, which includes a first inverter having an input terminal connected with the bit line; and a second inverter which has an input terminal connected with an output terminal of the first inverter and an output terminal connected with the bit line and is enabled/disabled in response to a sensing control signal.Type: GrantFiled: July 30, 2007Date of Patent: August 4, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Myeong-O Kim, Soo-Hwan Kim, Jong-Cheol Lee
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Publication number: 20090040853Abstract: A method and semiconductor memory device for precharging a local input/output line. The semiconductor memory device, which may have an open bit line structure, transmits data through local input/output lines that are coupled to bit lines of first to n-th memory cell array blocks (n being a natural number). The semiconductor memory device may include a precharge unit configured to generate a plurality of precharge signals and a controller configured to control precharging of the at least one local input/output line responsive to block information corresponding to activation of at least one of the memory cell array blocks and responsive to at least one of the precharge signals.Type: ApplicationFiled: August 6, 2008Publication date: February 12, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myeong-O KIM, Byung-Chul KIM, Yong-Gyu CHU
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Publication number: 20080159037Abstract: A semiconductor memory device including a bit line sense amplifier for amplifying a voltage corresponding to a charge stored in a capacitor of a memory cell and outputting an amplified voltage and an I/O sense amplifier for receiving the output of the bit line sense amplifier, amplifying a voltage level of the output and outputting an amplified voltage level is disclosed.Type: ApplicationFiled: December 20, 2007Publication date: July 3, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Jong-Cheol Lee, Myeong-O Kim
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Publication number: 20080151664Abstract: A sense amplifier circuit of a semiconductor memory device and a method of operating the same, in which the sense amplifier circuit includes a bit line sense amplifier connected with a bit line to sense and amplify a signal of the bit line, and a calibration circuit calibrating a voltage level of the bit line based on a logic threshold value of the bit line sense amplifier. The bit line sense amplifier senses and amplifies the signal of the bit line after the voltage level of the bit line is calibrated. The bit line sense amplifier may include a 2-stage cascade latch, which includes a first inverter having an input terminal connected with the bit line; and a second inverter which has an input terminal connected with an output terminal of the first inverter and an output terminal connected with the bit line and is enabled/disabled in response to a sensing control signal.Type: ApplicationFiled: July 30, 2007Publication date: June 26, 2008Inventors: Myeong-O Kim, Soo-Hwan Kim, Jong-Cheol Lee